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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

Power/Performance Bits: May 21
By Jesse Allen - 21 May, 2019 - Comments: 0

More speculative vulnerabilities Security researchers at the Graz University of Technology, KU Leuven, Cyberus Technology, and Worcester Polytechnic Institute point to two new speculative execution vulnerabilities related to Meltdown and Spectre. The first, which they dubbed ZombieLoad, uses a similar approach to Meltdown. After preparing tasks in parallel, the processor needs to discard th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2019 - Comments: 0

Cadence's Sean Dart shares an example of the kind of optimizations HLS tools can perform that would be difficult to find and implement by hand-coding RTL. Synopsys' Taylor Armerding takes a look at three cybersecurity initiatives from the U.S. government, from an IoT bill to improved voting machines, and whether they're likely to work. In a video, Mentor's Colin Walls points to why flashi... » read more

Power/Performance Bits: May 14
By Jesse Allen - 14 May, 2019 - Comments: 0

Detecting malware with power monitoring Engineers at the University of Texas at Austin and North Carolina State University devised a way to detect malware in large-scale embedded computer systems by monitoring power usage and identifying unusual surges as a warning of potential infection. The method relies on an external piece of hardware that can be plugged into the system to observe and m... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 May, 2019 - Comments: 0

Tools & IP Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduct... » read more

Blog Review: May 8
By Jesse Allen - 08 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that the threat of cyber war on the financial system is a real possibility and points to four major vulnerability concerns. Cadence's Meera Collier takes a look at bees and technology, from smart hives to sensors that can be carried on the insects' backs. Mentor's Brent Klingforth argues that electrical and mechanic designers need to seamlessly share infor... » read more

Power/Performance Bits: May 6
By Jesse Allen - 06 May, 2019 - Comments: 0

Compressing objects Computer scientists at MIT propose a way to improve data compression in memory by focusing on objects rather than cache lines. "The motivation was trying to come up with a new memory hierarchy that could do object-based compression, instead of cache-line compression, because that's how most modern programming languages manage data," said Po-An Tsai, a graduate student at... » read more

Week In Review: Design, Low Power
By Jesse Allen - 03 May, 2019 - Comments: 0

ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR's tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. "ANSYS brings industry-leading electronic simulation capabiliti... » read more

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