Week In Review: Design, Low Power

SLAM DSP; DPU for VR; protocol debugging.


Tools & IP
Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements including 3D DMA, compression and a 256-bit AXI interface. The company says it provides up to 2X greater AI and floating-point performance in the same area compared to its predecessor.

Arm uncorked the Mali-D77 display processor IP. Targeting VR applications, Mali-D77 offloads specific compute functions from the GPU, in particular, Lens Distortion Correction, Chromatic Aberration Correction, and Asynchronous Timewarp. The company says the use of a DPU for VR can provide 40% DRAM bandwidth reduction and provide a 12% power savings compared to a GPU alone. It can also be integrated into a common SoC platform with existing developer ecosystems for switching across multiple devices.

SmartDV announced a new protocol debugger, Smart ViPDebug, to reduce debug time by rapidly identifying violations. It fully encapsulates protocol specifications by eliminating the need for in-depth protocol knowledge and links a visual waveform display with a transaction log for discovery of violations and causes. An error detection mode highlights violations in the waveform display and log file.

Wave Computing will include the MIPS32 microAptiv cores in the newest release of MIPS Open program components. The MIPS32 microAptiv core is a low power, real-time solution for MCUs and entry-level embedded market applications. The Verilog RTL is now available to download without any license fees or royalties.

Samsung Foundry’s hard and soft design IP is now marketed, licensed, and supported through Silvaco. The suite of IP includes wired and high-speed interfaces, analog and mixed-signal blocks, and advanced security hard/soft cores. The initial offering of hard design IP is for the 14nm process node and is expected to extend to advanced technology nodes at 11nm, 10nm and 8nm, as well as mature planar technologies such as 28nm.

Amphion Semiconductor added a hardware based AV1 decoding extension to its Malone family of high performance video decoder IP. The standard configuration adds AV1 4Kp60 (UHD) decode capability to the other 13 formats already supported in the core including VP9, HEVC/H.265 and AVC/H.264. The architecture is also scalable to configurations which support higher resolutions, such as 8K, or higher frame rates, such as 120/240fps.

Tape Outs & Certifications
eSilicon has a large 2.5D FinFET ASIC targeting the 5G infrastructure market entering final product qualification. The design is over 600mm2, contains multiple HBM2 memory stacks on a silicon interposer, employs over 100 lanes of SerDes, and contains over 800Mb of embedded SRAM. The ASIC is a collaboration that included ASE for the advanced package, Rambus for the high-performance SerDes, Samsung for the 14nm FinFET ASIC fabrication and HBM memory stacks, and UMC for the silicon interposer.

Cadence taped out 112G long-reach SerDes IP on Samsung Foundry’s 7nm Low Power Plus (7LPP) process. It utilizes PAM-4 signaling, offers programmable power configurations, backward compatibility with legacy equipment, and targets 100G, 400G and 800G networks in data center and networking applications.

Arm, Samsung Foundry, Cadence, and Sondrel teamed up on a 28nm FD-SOI embedded MRAM (eMRAM) IoT test chip and development board. The Musca-S1 test chip demonstrates a combination of on-chip power control, Samsung Foundry’s Reverse Body Biasing (RBB), and eMRAM non-volatile memory power shutdown and can run Arm’s Mbed OS and Pelion IoT platform.

Cadence also taped out DDR5/4 PHY IP on the Samsung 7nm Low Power Plus (7LPP) process, GDDR6 PHY IP on the Samsung 14nm Low Power Plus (14LPP) process and 2.4G High-Bandwidth Memory 2 (HBM2) PHY IP on the Samsung 10nm Low Power Plus (10LPP) process, which has been recharacterized as the 8nm Low Power Plus (8LPP) process. Additionally, Cadence’s PHY IP for GDDR6 saw silicon success on the Samsung 7LPP process.

ANSYS’ RedHawk and Totem multiphysics solutions were certified for Samsung Foundry’s latest 5nm Low Power Early (5LPE) process technology. The certification includes extraction, power integrity and reliability, signal and power grid electromigration, as well as thermal analysis and signoff with self-heat and statistical EM budgeting.

Cadence’s custom and analog/mixed-signal IC design flow was certified for Samsung Foundry’s 28nm FD-SOI (28FDS) process technology.

Canaan Creative utilized Moortec’s In-Chip Monitoring Subsystem IP for Process, Voltage and Temperature Sensing in mass production of an HPC ASIC on TSMC’s 7nm process. Canaan cited the quality of the IP and customer support.

Black Sesame Technologies licensed Arteris IP’s FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package for use in its next-generation automotive ADAS that utilizes AI algorithms for autonomous driving capabilities. Black Sesame cited the need for data protection within the on-chip NoC interconnect to meet ISO 26262 ASIL B functional safety requirements.

Radio Frequency Systems (RFS) adopted ANSYS simulation solutions for its 5G antenna designs. RFS cited a reduction in simulation time from four days to one hour.

Shimadzu Corporation chose Mentor’s Xpedition design flow software for the company’s entire electronic design process and its PCB design-through-manufacturing flow. Shimadzu, a manufacturer of analytical instruments and medical equipment, cited improved design quality and IP reuse, team collaboration, and integrated verification.

Synopsys and Elektrobit are working together to improve pre-silicon and pre-ECU hardware availability and software development for automotive tier 1 and OEM companies with a collaboration that uses Synopsys VDKs to port EB AUTOSAR operating systems to new automotive processors up to 12 months before silicon availability. The solution has been used to create a virtual development environment demonstrator using a virtual ECU based on NXP’s S32 Automotive Processing Platform.

Innovium selected Cadence’s Palladium Z1 Enterprise Emulation Platform and Protium S1 FPGA-Based Prototyping Platform for its high-performance, scalable TERALYNX Ethernet switch for the data center. Innovium cited the common, congruent flow enabling verification environment reuse and the ability to perform early software development.

Startup Agile Analog raised $5 million in its latest Pre-A funding round with Delin Ventures, firstminute Capital and MMC Ventures. Founded in 2017, Agile Analog will use the funding to expand the existing engineering team in Cambridge and deliver analog IP products.

Accellera UVM-AMS PWG Kickoff: May 22 in Munich, Germany. A meeting to assess industry interest in standardizing analog/mixed-signal extensions for UVM. Open to all, but registration is required.

ESD Alliance CEO Outlook: May 23 6:00 p.m. to 8:300 p.m. in Milpitas, CA. This year’s panelists extend across the semiconductor supply chain: John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. Attendance is free, but registration is required.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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