Week In Review: Design, Low Power

Formal plus ML; cycle-accurate trace; IP for AI.


Tools & IP
Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduction in memory usage.

UltraSoC added cycle-accurate trace capabilities to its embedded monitoring and analytics infrastructure, initially as part of its processor trace solution for RISC-V. Targeting SSDs, servers, and real-time applications, the cycle-accurate tracing allows for optimization of hardware and software at the level of single clock cycles.

eSilicon taped out a 7nm test chip to validate the latest release of the neuASIC IP platform, a library of IP that supports a wide range of functions found in artificial intelligence applications. IP on the test chip includes specialized memory and compute blocks to support near-memory compute applications, including low power memory for interfacing with MACs and large embedded SRAMs.

eSilicon also taped out a 7nm test chip to provide silicon validation of its PHY to support the new HBM2E JEDEC standard, JESD235B. The 7nm test chip, which includes a controller from Northwest Logic, will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block. HBM2E increases total capacity from 8GB in HBM2 to 16GB, bandwidth per pin from 2.4 Gb/s to 3.2 Gb/s and bandwidth per stack from 307.2 GB/s to 410 GB/s.

ClioSoft received Tool Confidence Level 1 (TCL1) certification from TÜV SÜD. The company’s designHUB ecosystem, SOS7 design-management platform, and Visual Design software were certified for use with ASIL A through ASIL D automotive design projects complying with ISO 26262.

Fudan Microelectronics Group selected Synopsys’ DesignWare Bluetooth Controller and PHY IP for its ultra-low-power general purpose MCUs for IoT applications. Fudan cited differentiated power, area, and ease of SoC integration.

Semidrive licensed Arteris IP’s FlexNoC Interconnect and the accompanying FlexNoC Resilience Package for use in ADAS and autonomous driving chips. Semidrive cited functional safety mechanisms as well as performance, power consumption and die area requirements as part of the decision.

Wave Computing named Art Swift as CEO. Currently the president of Wave’s MIPS business, Swift has also served as Vice Chair of the RISC-V Foundation’s Marketing Committee and VP of Marketing and Business Development for Esperanto Technologies, and is President of the prpl Foundation. Swift will replace Derek Meyer, who will continue to serve the company in an advisory capacity.

Accellera UVM-AMS PWG Kickoff: May 22 in Munich, Germany. A meeting to assess industry interest in standardizing analog/mixed-signal extensions for UVM. Open to all, but registration is required.

ESD Alliance CEO Outlook: May 23 6:00 p.m. to 8:300 p.m. in Milpitas, CA. This year’s panelists extend across the semiconductor supply chain: John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. Attendance is free, but registration is required.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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