Week In Review: Design, Low Power

Marvell buys GF’s ASIC biz; Achronix adds new FPGA family; OneSpin debuts RISC-V verification; Synopsys adds contextual power tool; Mentor uncorks AI kit.


Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera’s revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between GlobalFoundries and Marvell. The deal also includes Avera’s IP portfolio with high-speed SerDes, high-performance embedded memory, and advanced packaging technology. The transaction is expected to close by the end of Marvell’s fiscal year 2020.

SiFive is set to expand its IP roadmap after its acquisition of USB IP and personnel from Innovative Logic in Bengaluru, India. Innovative Logic has developed a variety of USB 2.0 and 3.0 soft IP cores as well as a few other pieces of IP. It also had a design services group. No word yet from SiFive, a company known for its implementation of the RISC-V open source processor architecture, about how it intends to use the IP.

Tools & IP
Achronix announced a new FPGA family targeting artificial intelligence/machine learning (AI/ML) and high-bandwidth data acceleration applications. The Speedster 7t family features a 2D network-on-chip (NoC) along with an array of machine learning processors, and high bandwidth connectivity including direct-attached GDDR6, 400G Ethernet, and PCI gen5, fabricated using TSMCs 7nm process. The processors support integer formats from 4 to 24 bits, and have direct support for TensorFlow’s 16-bit format.

Synopsys uncorked its ZeBu Power Analyzer solution for software-driven SoC power analysis to reduce the risk of missing critical power issues by enabling use of realistic software workloads rather than synthetic scenarios. It has been integrated with the PrimePower power signoff flow, enabling design teams to pinpoint and fix power issues. Synopsys also added the Datapath Validation (DPV) app as part of its VC Formal solution. The DPV app leverages HECTOR technology to deliver exhaustive formal verification closure on datapath-intensive designs. They claim that the app delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques for complex system-on-chip (SoC) designs.

OneSpin Solutions unveiled a formal RISC-V Verification App. The App is intended to exhaustively verify that RSIC-V cores are developed and integrated with zero bug escapes and guarantee full compliance with the ISA, even with the range of configuration options available. OneSpin says the automated solution needs only a few days to set up and only two hours to run on a complete core. In addition, OneSpin’s 360 EC-FPGA now supports three Intel FPGA families, Stratix 10, Arria 10, and Cyclone V using Intel Quartus software for synthesis and place-and-route. The company says the move to support FPGAs used in high-bandwidth applications meets demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs. The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist.

Mentor debuted an artificial intelligence/machine learning (AI/ML) development kit and added AI/ML enhancements to two tools. Catapult High-Level Synthesis (HLS) AI Toolkit and HLS ecosystem aim to jumpstart the development of machine learning IC architectures. The toolkit provides an object detection reference design and IP to help designers quickly find optimal power, performance and area implementations for neural network accelerator engines. Calibre is becoming an AI/ML infrastructure platform, and launched Calibre Machine Learning OPC (mlOPC) and Calibre LFD with Machine Learning.

Agnisys announced a way to generate UVM testbenches automatically with its Specta-AV tool. The company says generation of the complete UVM testbench architecture including sequence items, configurations, checkers, and coverage are all automated, generating code from a golden specification which synchronizes all design and verification activities. It can parse and generate code from a hierarchical register specification in IP-XACT, SystemRDL, Word, and Excel.

SmartDV released Verification IP to support Compute Express Link (CXL), a new high-speed CPU-to-device and CPU-to-memory interconnect for next-generation data centers. The VIP is fully compliant with revision 1.0 of the CXL Specification and supports all major verification languages and methodologies, including OVM, UVM, and SystemC. SmartDV also uncorked Verification IP for Ethernet Time-Sensitive Networking (TSN), an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks. The VIP features a complete set of protocols, and verification and productivity tools for verification closure of Ethernet-based designs used in real-time communications where timing and latency must meet critical time boundaries. It verifies a design’s MAC-to-PHY and PHY-to-MAC layer interfaces and works within a SystemVerilog, Verilog, Vera, or SystemC environment.

Arasan Chip Systems uncorked new MIPI CSI-2 v2.1 Tx and Rx IP Cores integrated with its MIPI C-PHY v.1.2 IP supporting speeds of up to 3.5gbps and D-PHY v2.1 supporting speeds of up to 4.5gbps. The CSI v2.1 IP supports data scrambling/descrambling, all data types, and virtual channel extension to support 16 VCs in DPHY mode and 32 VCs in CPHY mode. The MIPI D-PHY / C-PHY Combo IP is available off the shelf in 40nm, 28nm, 16nm and 12nm nodes.

CAST announced two extensions to its line of UDP/IP cores for lean Internet Protocol networking: an increase up to 32 channels for its existing 10G and 40G UDP/IP Hardware Protocol Stacks, and the upcoming release of a faster, 100G version of these IP cores. UDP operates without the error resiliency of TCP.

AnalogX released their silicon-proven, multi-protocol, 1 to 33Gbps AXLinkIO connectivity IP portfolio. The portfolio consists of AXDieIO that targets chiplet die-to-die applications, while AXLinkIO-SR and AXLinkIO-MR target chip-to-chip, chip-to-module and multi-chip connectivity and support protocols such as PCIe Gen1-5, JESD, OIF, CPRI, Ethernet and others. The company claims to have breached the 1 mW/Gbps power barrier in 16/12nm.

ClioSoft’s SOS7 design management platform has been integrated into Silvaco’s Analog Custom Design tool flow to provide design management, including revision control and release management, and multi-site team collaboration support for designers who use Silvaco’s Analog IC tool suite.

Arteris IP and Wave Computing are working together on a reference architecture for an Enterprise Dataflow Platform that links Arteris’ NoC interconnect and AI package IP technology with Wave Computing’s TritonAI 64 dataflow processing elements and cores to reduce latency and optimize the flow of information across SoCs. Additionally, Wave Computing licensed Arteris IP’s Ncore Cache Coherent Interconnect, FlexNoC interconnect IP, and accompanying FlexNoC AI Package for use in its AI-enabled chips for data center systems products.

Thinci deployed the Cadence Verification for its machine learning and AI SoC designs. Thinci cited a reduction of IP and block-level regression times, shortened turnaround time, and expansion of its verification capabilities to hardware and software co-verification.

Kudan will optimize its simultaneous localization and mapping (SLAM) software algorithms for Synopsys’ DesignWare ARC EV6x Embedded Vision Processor IP. The combined hardware-software solution accelerates the SLAM tasks of tracking and mapping that take input from LiDAR, Time of Flight (TOF) cameras, inertial measurement units (IMUs), or odometry data while reducing power consumption and memory resources. Synopsys also announced that TSMC’s Open Innovation Platform Virtual Design Environment with Synopsys tools is now certified and available on the Google Cloud Platform. TSMC took a 7nm reference design through Synopsys’ suite of tools. The tests met TSMC’s requirements for security, runtime, and quality of results.

Numbers & People
Synopsys reported second quarter financial results with revenue of $836.2 million, up 7.6% from the second quarter last year. On a GAAP basis, Q2 2019 income was $0.77 per share, up 14.9% from $0.67 per share in Q2 2018. Non-GAAP income was $1.16 per share, up 7.4% from $1.08 per share in the same quarter last year. “Whereas geopolitical tension has escalated, the overall customer environment for us is quite solid,” said co-CEO Aart de Geus. He added, “As a result of our strong first half execution, we are raising the top end of our annual revenue and non-GAAP earnings guidance for the year.”

Tuomas Hollman will take over as CEO of Minima Processor, a provider of dynamic margining IP for near-threshold voltage designs. A co-founder of the company, Hollman was formerly Minima’s executive vice president of products and business development. He previously held positions at MaxLinear, Exar Corporation, and TI.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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