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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Power/Performance Bits: Jan. 2
By Jesse Allen - 02 Jan, 2019 - Comments: 0

High-temp electronics Researchers at Purdue University, UC Santa Cruz, and Stanford developed a semiconducting plastic capable of operating at extreme temperatures. The new material, which combines both a semiconducting organic polymer and a conventional insulating organic polymer could reliably conduct electricity in up to 220 degrees Celsius (428 F). "One of the plastics transports the ch... » read more

Power/Performance Bits: Dec. 26
By Jesse Allen - 26 Dec, 2018 - Comments: 0

2nm memristors Researchers at the University of Massachusetts Amherst and Brookhaven National Laboratory built memristor crossbar arrays with a 2nm feature size and a single-layer density up to 4.5 terabits per square inch. The team says the arrays were built with foundry-compatible fabrication technologies. "This work will lead to high-density memristor arrays with low power consumption fo... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Dec, 2018 - Comments: 0

Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

Blog Review: Dec. 19
By Jesse Allen - 19 Dec, 2018 - Comments: 0

Cadence's Dave Pursley checks out the state of high-level synthesis and notes that 39% of survey respondents expect to be using it for the majority of designs within three years. In a video, Mentor's Colin Walls digs into how to measure RTOS performance with a focus on interrupt latency. Synopsys' Taylor Armerding chats with Chenxi Wang of Rain Capital to find what the security landscape will... » read more

Power/Performance Bits: Dec. 18
By Jesse Allen - 18 Dec, 2018 - Comments: 0

Solar storage Engineers at MIT, Georgia Institute of Technology, and the National Renewable Energy Laboratory designed a system to store renewable energy in vast amounts and deliver it back to the grid when power generation is low. The system stores excess electricity from solar or wind installations as heat using tanks of white-hot molten silicon, and then converts the light from the glowi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Dec, 2018 - Comments: 0

The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to not... » read more

Blog Review: Dec. 12
By Jesse Allen - 12 Dec, 2018 - Comments: 0

Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

Power/Performance Bits: Dec. 11
By Jesse Allen - 11 Dec, 2018 - Comments: 0

Internet of Ears for smart buildings Scientists at Case Western Reserve University proposed a new way for smart homes to determine building occupancy: sensors that 'listen' to vibration, sound, and changes in the existing ambient electrical field. "We are trying to make a building that is able to 'listen' to the humans inside," said Ming-Chun Huang, an assistant professor in electrical engi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Blog Review: Dec. 5
By Jesse Allen - 05 Dec, 2018 - Comments: 0

Mentor's Harry Foster digs into verification effectiveness in FPGA projects and what it means that so many non-trivial bugs escape into production. Cadence's Paul McLellan checks out an effort to integrate photonics with CMOS and find the tradeoffs in three different approaches, plus the view of photonics as applied to military aircraft. Synopsys' Richard Solomon shares some highlights on... » read more

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