Blog Review: Dec. 5

FPGA bug escapes; integrated photonics; AI needs new memories.


Mentor’s Harry Foster digs into verification effectiveness in FPGA projects and what it means that so many non-trivial bugs escape into production.

Cadence’s Paul McLellan checks out an effort to integrate photonics with CMOS and find the tradeoffs in three different approaches, plus the view of photonics as applied to military aircraft.

Synopsys’ Richard Solomon shares some highlights on the journey to PCIe 5.0 and the recent release of the Draft 0.9 specification.

Applied Materials’ Gill Lee argues that the role of memory is set to expand in the AI era and that even with improvements to traditional memories a range of new types and architectures will be needed.

VLSI Research’s Julian West looks at this year’s bumpy ride for critical subsystems, where a booming first half for the industry led to a sharp decline in the second as the market for fab equipment cooled.

ANSYS’ David Geb looks at simplifying thermal simulations by using thermal networks to represent electronic components as 1D models.

A Rambus writer points to the fundamental shortfall that undermines the security of blockchain solutions and the importance of protecting private keys.

Arm’s Ronan Synnott provides a tutorial on how to get started with Arm Development Studio and migrate Keil MDK and DS-5 projects to the new platform.

Nvidia’s Bob Sherbin checks out a startup that uses deep learning, signal processing, and customizable speech recognition technologies to provide a synthesized voice for those with speech impairments.

Intel’s Faith McCreary considers some of the pain points in IIoT and the transformation to Industry 4.0 plus five strategies for making it easier.

And don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling contends that the rate of innovation is causing upheaval across the chip industry.

Technology Editor Brian Bailey explores the sometimes wacky patent world.

OneSpin’s Raik Brinkmann observes that programmable SoCs are shaping up to be an important part of the chip landscape, but they face verification challenges.

Cadence’s Frank Schirrmeister looks at virtual platforms in the automotive design process, from OEMs to EDA.

Synopsys’ Manoz Palaparthi explains why cloud computing is becoming necessary in complex designs.

eSilicon’s Mike Gianfagna finds that high-performance computing is no longer limited to the ultra-high end of the market.

Mentor’s Satishkumar Balasubramanian argues that outdated methodologies hamper mixed-signal design success.

Semico Research’s Joanne Itow considers the difference a trade war can make.

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