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Blog Review: Dec. 19

State of HLS; integrating accelerators; measuring RTOS performance.

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Cadence’s Dave Pursley checks out the state of high-level synthesis and notes that 39% of survey respondents expect to be using it for the majority of designs within three years.

In a video, Mentor’s Colin Walls digs into how to measure RTOS performance with a focus on interrupt latency.

Synopsys’ Taylor Armerding chats with Chenxi Wang of Rain Capital to find what the security landscape will look like in 2019 and why privacy issues will play a big role.

Arm’s Balaji Venu explains the Arm Coherent Accelerator Interface (ACAI) framework that aims to make it easier to integrate hardware accelerators in an SoC environment.

Applied Materials’ Mehul Naik details the interconnect challenges that threaten to keep power and performance from scaling with area and cost as well as the importance of new materials in overcoming the bottleneck.

Intel’s Ron Wilson digs into blockchain and the difficulties in determining the workload they place on data centers and cloud providers.

Walt Custer of Custer Consulting Group warns that 2019 could be a volatile year and points to signs that electronic equipment growth has peaked for this business cycle, with the rest of the supply chain responding.

ANSYS’ Sandeep Sovani argues that better sensors, perceptive AI, and testing and validation of decision-making software are major challenges facing the development of Level 5 autonomous vehicles.

UltraSoC’s Aileen Smith predicts that RISC-V will provide a big boost to China’s SoC development.

Plus, don’t forget to check out the blogs featured in the latest Low Power-High Performance and Manufacturing & Process Technology newsletters:

Editor In Chief Ed Sperling contends that recent moves by Intel and others are driven by the intersection of three factors.

Synopsys’ Himanshu Bhatt and Shreedhar Ramachandra explains how to make sure subtle bugs do not escape in low power designs.

Mentor’s Hossam Sarhan digs into how 2D fracturing can provide accurate results in a timely manner.

Rambus’ Ken Wright looks at how to intelligently utilize multiple types of memory in a single subsystem.

Editor In Chief Ed Sperling questions what will drive the need for more transistor density.

Executive Editor Mark LaPedus encounters mysterious locations, codenames and process delays.

Applied Materials’ Gill Lee examines the need for innovations in materials and systems for next-gen computing.

SEMI’s Christian Dieseldorff contends that leading-edge investments could slow, while mature technologies continue to be robust.



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