Week In Review: Design, Low Power

AI accelerator with eMRAM; Wave frees MIPS; parasitics to 2nm.


Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles.

Arm expanded its line of automotive-focused IP with the addition of Cortex-A65AE. Designed for processing multiple streams of sensor data, the multithreaded processor can be used in lock-step mode connected to accelerators and includes integrated safety features as well as Split-Lock, which allows it to be used in applications of varying safety requirements.

Wave Computing will make the MIPS instruction set architecture open source next year. Under the program, called MIPS Open, participants will have full access to the most recent version (Release 6) of the 32-bit and 64-bit MIPS ISA free of charge and royalties, as well as SIMD and DSP extensions, MIPS Multi-Threading, MIPS MCU, and microMIPS. “The MIPS-based solutions developed under MIPS Open will complement our existing and future MIPS IP cores that Wave will continue to create and license globally as part of our overall portfolio of systems, solutions and IP,” said Lee Flanagin, Wave’s senior vice president and chief business officer. “This will ensure current and new MIPS customers will have a broad array of solutions from which to choose for their SoC designs, and will also have access to a vibrant MIPS development community and ecosystem.” More details will be made available in Q1 2019. Wave acquired MIPS in June 2018.

Bluespec released a new commercially supported open-source RISC-V processor. Flute is a configurable 5-stage application processor complementing the company’s previously released 3-stage Piccolo microcontroller, targeted at IoT. The initial release provides synthesizable Verilog for a bare metal RV32IMA core and a supervisor level RV64IMA core, which has been tested in Xilinx UltraScale/UltraScale+ boards. Future releases will add floating point and compressed instructions (RV32GC/RV64GC) and run Linux and FreeRTOS.

The Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB) ratified new modeling constructs to address timing and parasitic extraction at process nodes down to 2nm. The Liberty standard now provides better insight into the assumptions used for computation of dynamic power values in the library models. For the interconnect technology file (ITF), extraction modeling now addresses gate resistance for new device architectures, as well as patterning extensions on interconnect and trench contact structures. Both boards are sponsored by Synopsys, which has added the proposals to its design platform.

Modelithics and ANSYS are teaming up to develop a 3D electromagnetic simulation component model library for the design of wireless communication systems for 5G, smart devices, and IIoT. The models are defined by their physical geometry and material properties and can properly simulate interactions between components and their surrounding environment.

JEDEC updated the JESD235 High Bandwidth Memory (HBM) DRAM standard, extending the per pin bandwidth to 2.4 Gbps, adding a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updating the MISR polynomial options for these new configurations.

AI chip startup Graphcore closed a $200 million Series D funding round, with BMW i Ventures and Microsoft joining Robert Bosch, Dell Technologies, and Samsung Electronics as strategic investors. The round was led by the VC firm Atomico and new investor Sofina.

Synopsys updated its RSoft Photonic Component Design Suite with a new optical design workflow for nano-textured diffractive optical elements for smaller and more lightweight AR/VR devices with improved displays.

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