Week In Review: Design, Low Power

By Jesse Allen - 27 Nov, 2020 - Comments: 0

AI Mythic debuted its Analog Matrix Processor for edge AI applications such as smart home, AR/VR, drones, video surveillance, smart city, and industrial. The M1108 AMP combines 108 tiles made up of an array of flash cells and ADCs, a 32-bit RISC-V nano-processor, a SIMD vector engine, SRAM, and a high-throughput Network-on-Chip router. It uses 40nm technology and the company says typical power... » read more

Week In Review: Design, Low Power

By Jesse Allen - 21 Dec, 2018 - Comments: 0

Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

AI Accelerator Gyrfalcon Soars Post Stealth

By Kevin Fogarty - 12 Nov, 2018 - Comments: 0

Milpitas, Calif.-based startup Gyrfalcon Technology Inc. (GTI), which emerged from semi-stealth mode in September, recently announced the datacenter-focused second generation of its neural-network accelerator, which was first aimed at the endpoint. GTI is not alone: The endpoint market is growing. By 2022, 25% of endpoint devices will execute AI algorithms (inference for neural network appli... » read more

Week In Review: Design, Low Power

By Jesse Allen - 21 Sep, 2018 - Comments: 0

Tools & IP Cadence unveiled deep neural-network accelerator (DNA) AI processor IP, Tensilica DNA 100, targeted at on-device neural network inference applications. The processor is scalable from 0.5 TMAC (Tera multiply-accumulate) to 12 TMACs, or 100s of TMACs with multiple processors stacked, and the company claims it delivers up to 4.7X better performance and up to 2.3X more performance p... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Gyrfalcon Technology

Week In Review: Design, Low Power

Week In Review: Design, Low Power

AI Accelerator Gyrfalcon Soars Post Stealth

Week In Review: Design, Low Power