Week In Review: Design, Low Power

AI processors and platforms; Renesas offers its IP; functional safety analysis.


Tools & IP
Cadence unveiled deep neural-network accelerator (DNA) AI processor IP, Tensilica DNA 100, targeted at on-device neural network inference applications. The processor is scalable from 0.5 TMAC (Tera multiply-accumulate) to 12 TMACs, or 100s of TMACs with multiple processors stacked, and the company claims it delivers up to 4.7X better performance and up to 2.3X more performance per watt compared to other solutions with similar MAC array sizes. In particular, the processor’s engine deals with the inherent sparsity of neural networks by eliminating unnecessary loading and multiplying of zeros for power efficiency and compute reduction. The processor comes with a complete AI software platform.

Renesas is jumping in to the IP licensing market with a portfolio of more than 40 offerings, including are CPU cores (RX, SH, etc.), timer IP for motor applications, USB cores, and SRAM. In particular, the company sees its IP as useful to the AI, autonomous vehicle, and robot markets. Renesas says more licenses will be offered in response to demand.

ANSYS released the latest version of its simulation suite. Version 19.2 includes more capabilities for functional safety analysis of automotive semiconductors, new hybrid simulation techniques for PCB analysis, faster and more accurate CFD simulation, and simulation of autonomous vehicles.

eSilicon launched its new 7nm neuASIC IP platform for AI ASIC designs that need to adapt to changing AI algorithms. The platform includes a library of AI-targeted functions that can be combined and configured to create custom AI algorithm accelerators. Compiled, hardened and verified functions include 56G SerDes, HBM2 PHY, AI mega/giga cells, and convolution engine.

AI hardware startup Gyrfalcon Technology emerged from stealth mode with the announcement of its Matrix Processing Engine (MPE) designed for high-performance AI processing in IoT and edge devices. The company’s first product, the Lightspeeur 2801S accelerator, is a 7mm x 7mm 28nm ASIC that uses 300mW of power and provides 9.3 TOPS/W for processing audio and video input.

Mentor’s Xpedition and PADS Professional PCB design flows, including the Valor NPI and HyperLynx family of products, were certified by TÜV SÜD for functional safety at ISO 26262 Tool Confidence Level 1 for ASIL A through ASIL D.

LG Electronics chose Synopsys’ DesignWare HDMI 2.1 Controller IP with HDCP 2.3 content protection to implement secure, high-quality digital video and audio links in its latest generation of multimedia SoCs. LG cited features such as uncompressed 8K resolution with 60 Hz refresh rate and dynamic HDR, and is also using Synopsys’ Logic Libraries, Embedded Memories, USB, Mobile Storage, and Ethernet IP in the SoC.

Graphcore used Synopsys’ Design Platform in designing its Colossus intelligent processing unit (IPU) for AI workloads. Colossus uses graph computing with massively parallel, low-precision floating-point compute for higher compute density. Graphcore cited AI-focused optimization technologies that provided better power, performance, and area results, and faster design closure.

Digital Marketing Workshop 2.0: Oct. 3, 6 p.m. – 8:30 p.m. in Milpitas, CA. A workshop focused on three organizational shifts that are key to mastering digitally-driven marketing and sales and conducting marketing in an agile manner.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased an expanded roadmap for future products to be released at the show.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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