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Week In Review: Design, Low Power

Royalty-free I3C; CFET parasitic variation modeling; Intel funds analog IP generation.

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The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to notify masters of interrupts, dynamic address assignment, and standardized discovery.

Efinix will expand its product offering, adding a 200K logic element FPGA to its lineup with the Triton T200. The T200 targets AI-driven products, and its architecture has enough LEs, DSP blocks, and on-chip RAM to deliver 1 TOPS for CNN at INT8 precision and 5 TOPS for BNN, according to Efinix CEO Sammy Cheung. The company also released samples of its Trion T20 FPGA.

Faraday Technology released multi-protocol video interface IP on UMC 28nm HPC. The Multi-Protocol Video Interface IP solution supports both transmitter (TX) and receiver (RX). The transmitter allows for MIPI and CMOS-IO combo solutions for package cost reduction and flexibility, while the receiver combo PHY includes MIPI, LVDS, subLVDS, HiSPi, and CMOS-I/O to support a diversified range of interfaces to CMOS image sensors. Target applications include panel and sensor interfaces, projectors, MFP, DSC, surveillance, AR and VR, and AI.

Analog tool and IP maker Movellus closed a second round of funding from Intel Capital. Movellus’ technology automatically generates analog IPs using digital implementation tools and standard cells. The company will use the funds to expand its customer base and to increase its portfolio of PLLs, DLLs and LDOs for use in semiconductor and system designs at advanced process nodes.

Imec and Synopsys completed a comprehensive sub-3nm parasitic variation modeling and delay sensitivity study of complementary FET (CFET) architectures. The QuickCap NX 3D field solver was used by Synopsys R&D and imec research teams to model the parasitics for a variety of device architectures and to identify the most critical device dimensions and properties, which allowed for optimization of CFET devices for better power/performance trade-offs.

Credo utilized Moortec’s Temperature Sensor and Voltage Monitor IP to optimize performance and increase reliability in its latest generation of SerDes chips. Moortec’s PVT sensors are utilized in all Credo standard products which are being deployed on system OEM linecards and 100G per lambda optical modules. Credo cited ease of integration and reduced time-to-market and project risk.

Wave Computing selected Mentor’s Veloce Strato emulation platform for functional verification and validation of its latest Dataflow Processor Unit chip designs, which will be used in the company’s next-generation AI system. Wave cited capacity and scaling advantages, breadth of virtual use models, reliability, and determinism as behind the choice.

MaxLinear adopted Cadence’s Quantus and Tempus timing signoff tools in developing the MxL935xx Telluride device, a 400Gbps PAM4 SoC using 16FF process technology. MaxLinear estimated they got 2X faster multi-corner extraction runtimes versus single-corner runs and 3X faster timing signoff flow.

The European Processor Initiative selected Menta as its provider of eFPGA IP. The EPI, a collaboration of 23 partners including Atos, BMW, CEA, Infineon and ST, has the objective of co-designing, manufacturing and bringing to market a system that supports the high-performance computing requirements of exascale machines.



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