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Week In Review: Design, Low Power


Arm announced its new roadmap promising 30% annual system performance gains on leading edge nodes through 2021. These gains are to come from a combination of microarchitecture design to hardware, software and tools. They are branding this new roadmap 'Neoverse.' The first delivery will be Ares – expected in early 2019 – for a 7nm IP platform targeting 5G networks and next-generation cloud t... » read more

Blog Review: Oct. 17


Arm's Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption. Synopsys' Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays. Cadence's Paul McLellan shares tips on more effective market... » read more

Power/Performance Bits: Oct. 16


On-chip modulator Researchers at Harvard SEAS and Nokia Bell Labs boosted shrunk down an important component of optoelectronics with an on-chip modulator that is 100 times smaller and 20 times more efficient than current lithium niobite (LN) modulators. Lithium niobate modulators form the basis of modern telecommunications, converting electronic data to optical information in fiber optic ca... » read more

Week In Review: Design, Low Power


Deals AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP's FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories. Phison, a maker of NAND flash controller ICs, inked�... » read more

Blog Review: Oct. 10


In a video, Cadence's Megha Daga dives into sparsity in neural networks and how it affects bandwidth, performance, and power efficiency. In a video, Mentor's Colin Walls takes a look at efficient embedded code, and why that means different things at different times. Synopsys' Eric Huang argues that in the realm of video standards, HDMI, DisplayPort, and USB Type-C are set to continue comp... » read more

Power/Performance Bits: Oct. 9


Spray-on antenna Engineers at Drexel University developed a sprayable form of the 2D material MXene that can be used to create antennas on nearly any surface. The antennas perform as well or better than the ones currently used in mobile devices and RFID tags. The MXene titanium carbide can be dissolved in water to create an ink or paint. The exceptional conductivity of the material enables ... » read more

Week In Review: Design, Low Power


Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

Blog Review: Oct. 3


Applied's Buvna Ayyagari-Sangamalli notes that the requirements of AI are challenging the entire design ecosystem, and while new materials are necessary, so is keeping up the current pace of architecture and EDA development. Mentor's Joe Hupcey III digs into how to handle counters effectively with formal by reducing their size or replacing them with abstract models to allow formal engines to... » read more

Power/Performance Bits: Oct. 2


Photonic sensor Researchers at Washington University in St. Louis devised a way to record environmental data using a wireless photonic sensor resonator with a whispering-gallery-mode (WGM) architecture capable of resonating at light frequencies and also at vibrational or mechanical frequencies. Optical sensors are not affected by electromagnetic interference, a major benefit in noisy or har... » read more

Week In Review: Design, Low Power


Arm announced a new processor targeted at autonomous driving applications. The Cortex-A76AE is a superscalar, out-of-order processor that incorporates Split-Lock safety technology. Split-Lock allows CPU clusters in an a SoC to be configured either in ‘split mode’ for high performance, allowing two (or four) independent CPUs in the cluster to be used for diverse tasks and applications, or �... » read more

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