Blog Review: Oct. 17

Power in high-performance mobile; compression basics; memory market indicators.


Arm’s Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption.

Synopsys’ Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays.

Cadence’s Paul McLellan shares tips on more effective marketing from the recent ESD Alliance’s Digital Marketing Workshop, including why the new mode encourages customers to come to you rather than pursuing them immediately.

Mentor’s Vidya Neerkundar explains how a customer was able to use a hierarchical DFT flow but still perform physical implementation on the flat layout.

SEMI’s Sungho Yoon digs into key indicators that point to a weakening of the memory market and why China may bear the brunt of the impact.

UltraSoC’s Marcin Hlond shares observations from the recent ORConf 2018 event focused on open source digital, semiconductor and embedded systems and highlights a few projects worth keeping an eye on.

ANSYS’ Hakon Bull Hove shares how an engineering project was used to introduce the concepts of simulation and modeling, as well as project management, to a class of middle school students.

A Rambus writer considers two recent cyberattacks on port authorities, one hitting the Port of Barcelona and affecting the loading and unloading of boats while the Port of San Diego was hit with ransomware that limited services.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Editor In Chief Ed Sperling contends that for AI, inferencing is the next battleground.

Executive Editor Ann Steffora Mutschler observes that engineering teams are starting to make SoC design choices based on manufacturing effects.

Mentor’s Rohit Jain zeroes in on a new reuse methodology that shortens drawn-out design verification cycles.

Synopsys’ Himanshu Bhatt digs into a low power methodology that uses a combination of static and dynamic verification.

Fraunhofer’s Roland Jancke looks at using an integrated model-based flow for more efficient safety-aware design.

Rambus’ Mondeep Thiara argues that automotive chipmakers face requirements not found in other consumer electronics.

Cadence’s Lazaar Louis finds the move away from general-purpose CPUs is driving architectural innovation.

Flex Logix’s Geoff Tate notes that flexibility is critical for satellites that may be orbiting for 20 years.

Kandou’s Jeff McGuire argues that low power and high bandwidth over extremely short distances is key to SerDes for chiplets.

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