Week In Review: Design, Low Power

Arm’s roadmap; AI architecture exploration; SoC development IDE.


Arm announced its new roadmap promising 30% annual system performance gains on leading edge nodes through 2021. These gains are to come from a combination of microarchitecture design to hardware, software and tools. They are branding this new roadmap ‘Neoverse.’ The first delivery will be Ares – expected in early 2019 – for a 7nm IP platform targeting 5G networks and next-generation cloud to edge infrastructure. Synopsys released QuickStart Implementation Kits (QIKs), including scripts and reference guide, for Neoverse processors in 7nm process technology.

Synopsys uncorked a new tool for architecture exploration, analysis, and design. Focused primarily on AI-enabled SoCs, Platform Architect Ultra flexibly maps CNN algorithms and workloads to explore processing and memory architecture options. The tool provides for context-sensitive data entry and error checking as well as visual root-cause sensitivity analysis of candidate architectures. It also introduces a hierarchical design concept for fast creation and packaging of a design, including ready-to-map workloads, architecture models, and AI reference system, including CNN frameworks such as Caffe and TensorFlow.

UltraSoC launched an IDE that combines comprehensive debug, run control, and performance tuning with visualization and data science capabilities for SoC development. Based on Eclipse, UltraDevelop 2 allows for viewing and analysis of the interlinked behavior of hardware, firmware and software at any level of abstraction. New data science extensions offer capabilities such as anomaly detection, heat mapping and root cause analysis, and technology from Imperas and Percepio add complex debug and visualization capabilities.

Aldec added two new reference designs to its TySOM-3-ZU7EV embedded development kit. The first, an ADAS ‘Bird’s-Eye View’ reference design, works to provide a 360 degree surrounding view of the vehicle. It requires an FMC-ADAS daughter card and four fisheye cameras. The second, a 4k Ultra HD image transfer reference design, implements the QSFP+ interconnect standard. The TySOM-3-ZU7EV features a Xilinx Zynq UltraScale+ MPSoC device, which provides 64-bit processor (dual-core ARM Cortex) scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing.

Rambus will expand its Differential Power Analysis (DPA) Workstation to include the Riscure Inspector Fault Injection (FI) products in a comprehensive side-channel analysis platform. The platform provides an integrated suite of hardware and software for analyzing the vulnerabilities of cryptographic chips and systems to attacks such as fault, power and electromagnetic side-channel attacks.

Si2 has been working on an update to their Unified Power Model (UPM), which has received a boost from patented technology made available to them from IBM and GlobalFoundries. These contributions provide a new approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models contain multiple power contributors such as sub-threshold leakage, gate leakage, and dynamic power. UPM forms the basis for IEEE P2416, which is scheduled for balloting in early 2019.

DARPA selected Synopsys, along with Lockheed Martin and Analog Devices, for the Posh Open Source Hardware (POSH) program, which aims to create new innovation in analog mixed signal verification as part of its Electronics Resurgence Initiative (ERI). Synopsys will seek to develop critical signoff-quality emulation technology for mixed signal SoCs to enable faster time-to-market and improved quality of mixed-signal SoC designs for aerospace and defense applications.

Arm is teaming up with Cadence to execute bare metal pre-silicon verification compliance tests through the Arm Server Base System Architecture (SBSA) Compliance Suite using Cadence’s Palladium Z1 Enterprise Emulation Platform and Perspec System Verifier, allowing compliance testing on Arm-based server SoCs to be performed up to three months prior to Linux bring-up. The Arm SBSA Compliance Suite currently consists of 120 tests that can be run on a bare metal testbench generated by Perspec from a portable stimulus model of the design.

Iluvatar CoreX licensed Arteris IP’s FlexNoC Interconnect for a deep learning SoC application. Iluvatar CoreX cited design flexibility and support as well as power, performance and area results.

STMicroelectronics’ Microcontroller and Digital IC Groups selected Synopsys’ ASIP Designer Tool for key product designs. The tool automates the design of application-specific instruction set processors (ASIPs) and programmable accelerators. ST cited the ability to quickly develop complex ASIPs while maximizing design team efficiency.

Cadence’s Verification Suite is now available for Arm-based HPC server environments. Software tools in the suite have been run on the Hewlett Packard Enterprise Apollo 70 System using the Marvell’s ThunderX2 processor based on the Armv8-A architecture.

Linley Fall Processor Conference: Oct. 31 – Nov. 1 in Santa Clara, CA. Focused on processors for communications, IoT, servers, and advanced automotive systems, the conference features a number of sessions on AI architectures as well as a keynote covering technology and market trends.

ICCAD: Nov. 5-8 in San Diego, CA. The technical conference focused on emerging technology challenges in EDA features keynotes on IoT and Cloud systems, DARPA’s Electronics Resurgence Initiative, and the impact of technology trends on EDA tools and flows. Special sessions, tutorials, and workshops are also part of the program.

IEEE Rebooting Computing Week: Nov. 5-9 in Tysons, VA. The first two days will focus on the International Roadmap for Devices and Systems, while the International Conference on Rebooting Computing will be held the 7-9th. The conference focuses on novel computing approaches, including algorithms and languages, system software, system and network architectures, new devices and circuits, and applications of new materials and physics.

Phil Kaufman Award Ceremony and Dinner: Nov. 7, 6:30 – 9:30 p.m. in San Jose, CA. This year’s award honors Thomas W. Williams for his contributions to test automation including Level Sensitive Scan Design and subsequent enhancements to IC testing including adaptive scan.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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