Week In Review: Design, Low Power

Andes’ new processors; design partitioning; ANSYS’ new CTO.


AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP’s FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories.

Phison, a maker of NAND flash controller ICs, inked a patent license agreement with Rambus that gives Phison access to Rambus’ technologies for DRAM and NAND Flash memory controllers, as well as serial links. Additionally, Nvidia renewed a patent license agreement with Rambus, giving it access to patents including those covering memory controllers and serial links.

Aerospace and defense company Leonardo adopted Mentor’s Questa verification tool, VIP, and UVM framework for FPGA development. FPGAs are an important component of electronically scanned array radar systems. Leonardo cited reuse and scalability provided by the framework and VIP.

Mentor’s Calibre nmPlatform, Analog FastSPICE, Eldo Platform and Nitro-SoC place and route system have been certified for GlobalFoundries’ 22FDX FD-SOI process. Improvements for the process include an automated fill flow targeting both analog and RF IP blocks and full chips.

New releases
Andes announced a slate of new RISC-V based high-efficiency processors. The AndesCore A25/AX25 is targeted at Linux-based applications such as UAV, smart wireless communication, networking, video processing, ADAS, storage, data center, and machine/deep learning. The AndesCore N25F/NX25F can be used for a wide range of floating-point intensive applications including advanced motor control, satellite navigation, high-precision sensor fusion, and advanced smart meters. The A25/N25F are 32-bit CPU IP cores; AX25/NX25F are 64-bit cores. All of them are capable of operating over 1.2 GHz at the worst-case corner of TSMC 28nm HPC+ process.

Si2 released the newest version of the OpenAccess standard API and reference database, Data Model 6. A key feature of DM6 is oaPartitions, which enables OpenAccess applications to access critical components of enormous designs as easily as opening much smaller designs. “The real power of DM6 comes from the new partitioning capability. By subdividing a complex design, OpenAccess provides simultaneous access to multiple partitions from separate processes. Applications can use oaPartitions to exploit the full compute power available on the user’s platform,” said Marshall Tiner, Si2 director of Production Standards.

Prith Banerjee joined ANSYS as CTO. Previously, Banerjee served as executive vice president and CTO of both Schneider Electric and ABB and founded EDA companies AccelChip and BINACHIP Inc. His research background includes Accenture Technology Labs and HP Labs, and he was dean of the College of Engineering at the University of Illinois at Chicago.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased an expanded roadmap for future products to be released at the show.

International SoC Conference: Oct. 17-18 in Irvine, CA. This conference will present sessions ranging from next-generation integration to battery-less memory systems. Keynote topics include 5G, autonomous driving, RISC-V, and machine learning.

Linley Fall Processor Conference: Oct. 31 – Nov. 1 in Santa Clara, CA. Focused on processors for communications, IoT, servers, and advanced automotive systems, the conference features a number of sessions on AI architectures as well as a keynote covering technology and market trends.

ICCAD: Nov. 5-8 in San Diego, CA. The technical conference focused on emerging technology challenges in EDA features keynotes on IoT and Cloud systems, DARPA’s Electronics Resurgence Initiative, and the impact of technology trends on EDA tools and flows. Special sessions, tutorials, and workshops are also part of the program.

IEEE Rebooting Computing Week: Nov. 5-9 in Tysons, VA. The first two days will focus on the International Roadmap for Devices and Systems, while the International Conference on Rebooting Computing will be held the 7-9th. The conference focuses on novel computing approaches, including algorithms and languages, system software, system and network architectures, new devices and circuits, and applications of new materials and physics.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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