Author's Latest Posts


Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse


Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

Flexible USB4-Based Interface IP Solution For AI At The Edge


Consumers have become accustomed to smart devices that are powered by advances in artificial intelligence (AI). To expand the devices’ total addressable market, innovative device designers build edge AI accelerators and edge AI SoCs that support multiple use cases and integration options. This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP so... » read more

Scaling Processor Performance And Safety To Meet Requirements For Next-Generation Safety-Critical Automotive Designs


This white paper proposes a state-of-the-art processor architecture targeting automotive safety systems that meets the requirements of such active safety systems delivering the required processing performance, providing the highest automotive safety integrity level (ASIL) while also significantly contributing to a reduction in overall cost of the systems through the use of artificial neural net... » read more

Securing Connected Medical Devices For FDA Submissions


The benefits and challenges of the Internet of Things (IoT) are especially evident in healthcare, thanks to increases in the volume and use of medical devices. Network-connected devices have greatly improved patient care by helping healthcare providers monitor vital signs, regulate medication dosages, improve diagnostics, and ultimately improve patient outcomes while lowering costs. This whi... » read more

Raising The Bar With The Next Generation Of AI For Chip Design


The semiconductor industry is enjoying renewed growth despite chip shortages plaguing everything from cars to kitchen appliances. But while the chips themselves continue to get faster and smarter, the chip design process itself hasn’t changed that much in 20+ years. It typically takes 2-3 years to design a chip with a large engineering team and tens or hundreds of millions of dollars to get a... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage


Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers


Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization


Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

The 5 Essential Elements Of A Successful Software Security Initiative


Every organization that develops or integrates software needs a software security initiative—a blend of people, processes and tools that ensures applications and the data they process are secure. As customers, regulators, executives and boards of directors start asking for evidence of a formal approach to software security, organizations are trying to determine where to start, how to construc... » read more

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1


In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

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