Why embedding in-chip monitoring IP is an essential step to maximize performance and reliability and minimize power, or a combination of these objectives
The latest SoCs on advanced semiconductor nodes especially FinFET, typically include a fabric of sensors spread across the die and for good reason. But why and what are the benefits? This article explores some of the key applications for In Chip monitoring and why embedding In Chip monitoring IP is an essential step to maximize performance and reliability and minimize power, or a combination of these objectives. As SoC developers migrate to new smaller geometry nodes they enjoy considerable benefits of higher logic density, faster performance and lower power. However, the challenges also increase and need addressing in the light of the objectives to maximize performance, minimize power or optimize reliability or some combination of these, depending on the end application. One of the key challenges is the ‘end of Dennard Scaling’ as highlighted recently by John Hennessy at the AI hardware summit 2019. This is referring to the fact that since the mid 2000s as one migrates from one node to the next, the power per unit silicon area is no longer remaining roughly constant but in fact has been steadily increasing. When combined with a trend to very large chips, even approaching reticle size and the introduction of FinFETs which have more difficult thermal properties through their 3D structure, it doesn’t require much imagination to predict chips can potentially develop hotspots/thermal problems and IR drop issues. The other reasonably well known trend is of increased process variation, not just from chip to chip but within die. In the following sections of this article, I will explore how in chip monitoring IP can help address these challenges using process, voltage and temperature (PVT) monitors.
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