Author's Latest Posts

Solving The ASIC Prototype Partition Problem With Synopsys ProtoCompiler
By Synopsys - 28 Jan, 2015 - Comments: 0

When developing a multi-FPGA prototype of an ASIC or SoC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that... » read more

Designing the Right Architecture
By Synopsys - 14 Jan, 2015 - Comments: 0

Designing the right architecture of a multi-processor SoC for today's sophisticated electronic products is a challenging task. The most critical element for meeting the performance requirements of the entire system is the interconnect and memory architecture. These SoC infrastructure IP components are highly configurable and need to be customized to the communication needs of all the other modu... » read more

Using VDKs For Automotive Systems Development
By Synopsys - 17 Dec, 2014 - Comments: 0

The software content of automotive systems found in powertrain, chassis, safety, body and advanced driver assistance systems (ADAS) application is increasing. At the same time, the pressure to accelerate development time lines, improve reliability and maintain/reduce costs is also increasing. Automotive OEM, Tier 1 and semiconductor companies involved in embedded software development, integrati... » read more

Real-Time Trace: A Better Way To Debug Embedded Applications
By Synopsys - 03 Dec, 2014 - Comments: 0

Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This white paper shows the benefits of debugging with ‘real-time trace’... » read more

A Method To Quickly Assess The Analog Front-End Performance In Communication SoCs
By Synopsys - 19 Nov, 2014 - Comments: 0

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and oper... » read more

A Method To Quickly Assess The Analog Front-End Performance In Communication SoCs
By Synopsys - 05 Nov, 2014 - Comments: 0

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and oper... » read more

Extending Digital Verification Techniques For Mixed-Signal SoCs With VCS AMS
By Synopsys - 22 Oct, 2014 - Comments: 0

The growth in mixed-signal system-on-chip (SoC) designs is driven by many factors, including cost, performance and power consumption. This is fueled by many industry segments, including mobile communication, automotive, imaging, medical, networking and power management. The convergence of analog and digital blocks within the same die is driving the need for SoC design teams to adopt new verific... » read more

Meeting The USB IP Requirements Of SoC Designs From 180-nm To 14/16nm FinFET
By Synopsys - 08 Oct, 2014 - Comments: 0

The ubiquitous USB standard provides data and charging capabilities to a multitude of consumer and enterprise products. USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper ad... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

How VXLAN-Based Ethernet IP Solves Cloud Computing Network Bottlenecks
By Synopsys - 10 Sep, 2014 - Comments: 0

Network virtualization technologies running over optimized Ethernet IP are enabling cloud computing data centers to expand and support the growing amount of internet traffic. Hyperscale cloud data centers are driving requirements for new network overlay protocols such as Virtual Extensible LAN (VXLAN) running over Ethernet. This whitepaper discusses in detail the benefits of VXLAN and how it ca... » read more

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