Solving The ASIC Prototype Partition Problem With Synopsys ProtoCompiler

How to deal with constantly changing RTL and still build and debug in the allotted time.

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When developing a multi-FPGA prototype of an ASIC or SoC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that you can build and debug in the allotted time. And every week the RTL changes, and sometimes it seems that every decision you make forces you to revisit all the decisions that came before. There is a better way.

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