Author's Latest Posts


Using Silicon Photonics To Reduce Latency On Edge Devices


A new technical paper titled "Delocalized photonic deep learning on the internet’s edge" was published by researchers at MIT and Nokia Corporation. “Every time you want to run a neural network, you have to run the program, and how fast you can run the program depends on how fast you can pipe the program in from memory. Our pipe is massive — it corresponds to sending a full feature-leng... » read more

Bottoms Up: Arranging Nanoscale Particles On A Silicon Chip (Or Other Materials) Without Damage


A new research paper titled "Nanoparticle contact printing with interfacial engineering for deterministic integration into functional structures" was just published by researchers at MIT. “This approach allows you, through engineering of forces, to place the nanoparticles, despite their very small size, in deterministic arrangements with single-particle resolution and on diverse surfaces, ... » read more

Technical and Structural Approaches To Centralize Automotive E/E Architectures


A technical paper titled "Methodical Approach for Centralization Evaluation of Modern Automotive E/E Architectures" was published by researchers at University of Stuttgart and Daimler Truck AG. Abstract: "Centralization is considered as a key enabler to master the CPU-intensive features of the modern car. The development and architecture change towards the next generation car is influenced ... » read more

New Class of Electrically Driven Optical Nonvolatile Memory


A new technical paper titled "Electrical Programmable Multi-Level Non-volatile Photonic Random-Access Memory" was published by researchers at George Washington University, Optelligence, MIT, and the University of Central Florida. Researchers demonstrate "a multi-state electrically-programmed low-loss non-volatile photonic memory based on a broadband transparent phase change material (Ge2Sb2S... » read more

3D Racetrack Memory Device (Max Planck)


A new technical paper titled "Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures" was published by researchers at Max Planck Institute of Microstructure Physics in Halle, Germany. "Magnetic racetrack memory encodes data in a series of magnetic domain walls that are moved by current pulses along magnetic nanowires. To date, most studies have focuse... » read more

Active Learning to Reduce Data Requirements For Defect Identification in Semiconductor Manufacturing


A new technical paper titled "Exploring Active Learning for Semiconductor Defect Segmentation" was published by researchers at Agency for Science, Technology and Research (A*STAR) in Singapore. "We identify two unique challenges when applying AL on semiconductor XRM scans: large domain shift and severe class-imbalance. To address these challenges, we propose to perform contrastive pretrainin... » read more

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System


A technical paper titled "RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory" was published by researchers at ETH Zürich, KMUTNB, NTUA, and University of Toronto. Abstract: "Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-graine... » read more

Wearable Electrotactile Rendering System w/High Spacial resolution, Rapid Refresh


A new technical paper titled "Super-resolution wearable electrotactile rendering system" was published by researchers at City University of Hong Kong (CityU) and Tencent Technology's Robotics X Laboratory. "Here, we present a wearable electrotactile rendering system that elicits tactile stimuli with both high spatial resolution (76 dots/cm2) and rapid refresh rates (4 kHz), because of a prev... » read more

Hardware Trojan Inserted Inside A RISC-V Based Automotive Telematics Control Unit


A new technical paper titled "On the Feasibility of Remotely Triggered Automotive Hardware Trojans" was written by researchers at Georgia Tech. "In this paper, we discuss how Hardware Trojans can act as the physical access intermediates to allow the remote triggering of malicious payloads embedded in ECUs, through seemingly benign wireless communication. We demonstrate a proof of concept ECU... » read more

Memory-Computation Decoupling Execution To Achieve Ideal All-Bank PIM Performance


A new technical paper titled "Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling" was published by researchers at Korea University. "This paper proposed the memory-computation decoupled PIM architecture to provide the performance comparable to the all-bank PIM while preserving the standard DRAM interface, i.e., DRAM commands, powe... » read more

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