Author's Latest Posts


Visual Fault Inspection Using A Hybrid System Of Stacked DNNs


A technical paper titled "Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks" was published by researchers at Chemnitz University of Technology (Germany). According to the paper, "this contribution introduces a novel hybrid multistage system of stacked deep neural networks (SH-DNN) which allows the localization... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips


A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Functional-Engineered MXene Transistors


A new technical paper titled "High-throughput design of functional-engineered MXene transistors with low-resistive contacts" was published by researchers at Indian Institute of Science (IISc) Bangalore. Abstract (partial): "Two-dimensional material-based transistors are being extensively investigated for CMOS (complementary metal oxide semiconductor) technology extension; nevertheless, down... » read more

Cybersecurity & FPGA Devices


A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

Spin–Orbit Qubit With A Single Hole Electrostatically Confined In A Natural Silicon Metal-Oxide-Semiconductor Device


A new technical paper titled "A single hole spin with enhanced coherence in natural silicon" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however,... » read more

FP8: Cross-Industry Hardware Specification For AI Training And Inference (Arm, Intel, Nvidia)


Arm, Intel, and Nvidia proposed a specification for an 8-bit floating point (FP8) format that could provide a common interchangeable format that works for both AI training and inference and allow AI models to operate and perform consistently across hardware platforms. Find the technical paper titled " FP8 Formats For Deep Learning" here. Published Sept 2022. Abstract: "FP8 is a natural p... » read more

More Efficient On-Chip Laser Frequency Comb (Harvard)


A new technical paper titled "High-efficiency and broadband on-chip electro-optic frequency comb generators" was published by researchers at Harvard, Stanford, Caltech, and Hyperlight. The research claims the electro-optic frequency device is 100% more efficient and has 2X the bandwidth of previous technology.    According to Harvard's news release, "the latest research applies the two con... » read more

Graph-Based, Formal Equivalence Checking Method


A new research paper titled "Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits" was published by researchers at University of Bremen and DFKI GmbH. Abstract: "Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level met... » read more

Implementations of 2D Material-Based Devices For IoT Security


A new research paper titled "Application of 2D Materials in Hardware Security for Internet-of-Things: Progress and Perspective" was published by researchers at National University of Singapore and A*STAR. The paper explores the "implementation of hardware security using 2D materials, for example, true random number generators (TRNGs), physical unclonable functions (PUFs), camouflage, and ant... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)


A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

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