Author's Latest Posts


Syscall Attacks on PKU-based Isolation Systems (Graz University of Technology)


This technical paper titled "Jenny: Securing Syscalls for PKU-based Memory Isolation Systems" was presented by researchers at Graz University of Technology (Austria) at the USENIX Security Symposium in Boston in August 2022. Abstract: "Effective syscall filtering is a key component for withstanding the numerous exploitation techniques and privilege escalation attacks we face today. For exam... » read more

Side-Channel Attack “Binoculars” Exploits Interactions Between HW Page Walk Operations & Other Memory Operations


New technical paper titled "Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker" was presented by researchers at University of Illinois Urbana-Champaign and Tel Aviv University at the USENIX Security Symposium in Boston in August 2022. Abstract: "Microarchitectural side channels are a pressing security threat. These channels are created when programs modulate hardw... » read more

Vehicle Security: Post-Quantum Security to the CAN Network


This new technical paper titled "PUF-Based Post-Quantum CAN-FD Framework for Vehicular Security" is published by researchers at University of Tennessee. Abstract "The Controller Area Network (CAN) is a bus protocol widely used in Electronic control Units (ECUs) to communicate between various subsystems in vehicles. Insecure CAN networks can allow attackers to control information between vit... » read more

Assessing & Simulating Semiconductor Side-Channel or Unintended Data Leakage Vulnerabilities


This research paper titled "Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification" from researchers at Ansys, National Taiwan University and Kobe University won the best paper award at IEEE's International Symposium on Hardware Oriented Security and Trust (HOST). The paper presents a new tool "to assess unintended data leakage vulnerabilities... » read more

Prefetch Side Channels Undermine the Isolation Between User and Kernel Space on AMD CPUs


This new technical paper titled "AMD Prefetch Attacks through Power and Time" is from researchers at Graz University of Technology and CISPA Helmholtz Center for Information Security. Note, this is a prepublication paper for the USENIX Security Symposium in Boston in August 2022.   This paper includes countermeasures and mitigation strategies, and the paper indicates that the findings were di... » read more

Reservoir Computing HW Based on a CMOS-Compatible FeFET


A new technical paper titled "Reservoir computing on a silicon platform with a ferroelectric field-effect transistor" was published by researchers at the University of Tokyo. Researchers report "reservoir computing hardware based on a ferroelectric field-effect transistor (FeFET) consisting of silicon and ferroelectric hafnium zirconium oxide. The rich dynamics originating from the ferroelec... » read more

All-Solid-State Batteries: Substantial Deterioration of ASSBs Can Occur After High-Temperature Storage


New technical paper titled "Detrimental effect of high-temperature storage on sulfide-based all-solid-state batteries" was just published by researchers at Seoul National University, National Synchrotron Radiation Research Center (Taiwan), and Battery Material Lab at the Samsung Advanced Institute of Technology. According to this AIP article, "The team found storage as low as 70 degrees Cels... » read more

Securing Heterogeneous Integration at the Chiplet, Interposer, and System-In-Package Levels (FICS-University of Florida)


A new research paper titled "ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance" was published by researchers at the Florida Institute for Cybersecurity (FICS) Research, University of Florida. Abstract "The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Pa... » read more

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores


This new technical paper titled "RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs" was published by researchers at University of Bologna and ETH Zurich. According to their abstract: "One of the key stumbling stones is the need for parallel floating-point operations, which are considered unaffordable on sub-100 mW extre... » read more

Fully CMOS-compatible Ternary Inverter with a Memory Function Using Silicon Feedback Field-Effect Transistors (FBFETs)


New technical paper titled "New ternary inverter with memory function using silicon feedback field-effect transistors" was published from researchers at Korea University. Abstract: In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a pos... » read more

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