Author's Latest Posts

Repurposing Josephson Junctions At The Cell Boundaries For Fan-out (UCSB)
By Technical Paper Link - 16 Dec, 2022 - Comments: 0

A technical paper titled "Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions" was published by researchers at UC Santa Barbara.  The paper received an award at the Applied Superconductivity Conference in Oct 2022 and was highlighted in this UCSB news article. Abstract: "Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lo... » read more

Safeguarding SRAMs From IP Theft (Best Paper Award)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Beware of Discarding Used SRAMs: Information is Stored Permanently" was published by researchers at Auburn University. The paper won "Best Paper Award" at the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) Oct. 25-27 in Huntsville. Abstract: "Data recovery has long been a focus of the electronics industry for decades by s... » read more

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies" was published by researchers at UT Austin and NVIDIA. "This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design cons... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Graphene Devices: Suppressing Vibrations By Adding Vibrations (FLEET)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Passivating Graphene and Suppressing Interfacial Phonon Scattering with Mechanically Transferred Large-Area Ga2O3" was published by researchers at ARC Centre of Excellence in Future Low-Energy Electronics Technologies (FLEET), Monash University and University of Melbourne. According to FLEET's news article, the research found: -Ultra-thin, liquid-metal-printed oxid... » read more

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design
By Technical Paper Link - 14 Dec, 2022 - Comments: 0

A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Leveraging Multi-Agent RL for Microprocessor Design Space (Harvard, Google)
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A new technical paper titled "Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration" was published by researchers at Harvard University and Google research groups. Abstract "Microprocessor architects are increasingly resorting to domain-specific customization in the quest for high-performance and energy-efficiency. As the systems grow in complexity, fine-tuning arch... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)
By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

New Method to Measure, At The Wafer Scale, Direct Bonding Energies (CEA-LETI)
By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "Double cantilever beam bonding energy measurement using confocal IR microscopy" was published by researchers at Univ. Grenoble Alpes, CEA-LETI and SOITEC, Parc Technologique des Fontaines. "A new technique is assessed in order to measure, at the wafer scale, direct bonding energies. It is derived from the standard Double Cantilever Beam (DCB) method and uses int... » read more

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