Author's Latest Posts

Techniques For FSM Design And Verification
By Various Writers - 12 Sep, 2012 - Comments: 0

Large system-on-chip (SoC) designs contain many finite state machines (FSMs) that interact with data paths, memories, and other components. Although FSMs are critical building blocks many designers lack an understanding of their role and impact on design quality and validation effort. FSMs are a source of functional bugs in SoCs. They can cause poor timing, power, and performance. Although v... » read more

Computational Lithography
By Various Writers - 31 Aug, 2012 - Comments: 0

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year. To download this white paper, click here. » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

FPGA Design And Verification in Mechatronic Applications
By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?
By Various Writers - 23 Aug, 2012 - Comments: 0

It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

Mixed-Signal IP Design Challenges In 28nm Process And Beyond
By Various Writers - 23 Aug, 2012 - Comments: 0

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes. This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of ... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept (Part One)
By Various Writers - 23 Aug, 2012 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

Challenges For Patterning Process Models Applied To Large Scale
By Various Writers - 16 Aug, 2012 - Comments: 0

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist... » read more

2012 IP Challenges For The Semiconductor Industry
By Various Writers - 16 Aug, 2012 - Comments: 0

A company’s intellectual property (IP) is fundamental to its ability to innovate, develop new technologies and methods, and move forward in a competitive industry. SEMI is acutely aware that what distinguishes its key industries from many others is the relatively high percent of revenue that is reinvested into R&D. On average, semiconductor equipment and materials companies invest 10-... » read more

An Automated Approach To RTL Memory BIST Insertion And Verification
By Various Writers - 09 Aug, 2012 - Comments: 0

ASIC vendors have been traditionally incorporating built-in self test (BIST) and repair solutions in their customers' gate level netlist. This used to be the common industry practice for technology nodes of 65 nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make necessary connections. However, for... » read more

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