Techniques For FSM Design And Verification

Techniques For FSM Design And Verification


Large system-on-chip (SoC) designs contain many finite state machines (FSMs) that interact with data paths, memories, and other components. Although FSMs are critical building blocks many designers lack an understanding of their role and impact on design quality and validation effort.

FSMs are a source of functional bugs in SoCs. They can cause poor timing, power, and performance. Although verification tools can perform checks on FSMs, such as deadlock and unreachable states, these tools may not consider all aspects of FSM design styles.

This white paper discusses FSM functional issues, metrics, design styles, and systematic validation approaches. To download this white paper, click here.

Leave a Reply

(Note: This name will be displayed publicly)