An examination of the appropriate point in a design to insert BiST and the challenges of developing a proper methodology.
ASIC vendors have been traditionally incorporating built-in self test (BIST) and repair solutions in their customers’ gate level netlist. This used to be the common industry practice for technology nodes of 65 nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make necessary connections. However, for more advanced technology nodes it is becoming common practice to share a BIST engine with multiple memories, technology permitting, and insert hierarchical BIST IPs along with accurate connections.
This white paper examines problems with this approach, why BiST should be inserted at RTL and the challenges of an RTL MBiST insertion methodology. To download this white paper, click here.
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