System-Level Design

Yikes! Why Is My SystemVerilog Testbench So Slooooow?

When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.


It turns out thatĀ SystemVerilog != Verilog. OK, we all figured that out a few years ago as we started to build verification environments usingĀ IEEE 1800 SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, and randomization that have no analog (pardon the pun) in the IEEE 1364 Verilog language. But the syntax was a reasonable extension, many more designs needed advanced verification, and we had the Open Verification Methodology (OVM) followed by the standardizedĀ Accellera Systems Initiative Universal Verification Methodology (UVM) so thousands of engineers got trained on object-oriented programming. Architectures were created, templates were followed, and the verification IP components were built. Then they were integrated and the simulation speed took a nose dive. Yikes, why did that happen?

To view this white paper, click here.

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