When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
It turns out that SystemVerilog != Verilog. OK, we all figured that out a few years ago as we started to build verification environments using IEEE 1800 SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, and randomization that have no analog (pardon the pun) in the IEEE 1364 Verilog language. But the syntax was a reasonable extension, many more designs needed advanced verification, and we had the Open Verification Methodology (OVM) followed by the standardized Accellera Systems Initiative Universal Verification Methodology (UVM) so thousands of engineers got trained on object-oriented programming. Architectures were created, templates were followed, and the verification IP components were built. Then they were integrated and the simulation speed took a nose dive. Yikes, why did that happen?
To view this white paper, click here.
Foundry forms ASIC subsidiary as it focuses on 14nm/12nm and above.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Why auto tech companies are so concerned about interactions with humans.
Company’s push into deep learning opens door to a variety of new architectures, including tiles, advanced packaging and more customized solutions.
SoC bandwidth, integration expand as data centers use more FPGAs for machine learning.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.
What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.
What happens when companies are combined? The outcome often isn’t as good as the announcement.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
As complexity and device sizes rise, so does the need for an on-chip network.
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.
 |
 |
 |
 |
 |
 |
 |
 |
 |
|
Leave a Reply