How Much Verification Is Necessary?

By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?

By Various Writers - 23 Aug, 2012 - Comments: 0

It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

ESL Languages: Which One Is Right For Your Needs?

By Jon McDonald - 19 Feb, 2009 - Comments: 0

The question about ESL language is the right one comes up over and over again. As customers begin to understand the benefits of modeling and analysis at the system level, they must address this question as one of the first steps in getting started. What language should be used for ESL—SystemC, SystemVerilog, UML or M? Technically, you can create an ESL/TLM platform in any language yo... » read more

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tag: System Verilog

How Much Verification Is Necessary?

Yikes! Why Is My SystemVerilog Testbench So Slooooow?

ESL Languages: Which One Is Right For Your Needs?

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