Author's Latest Posts

Power Delivery Network (PDN) Verification Coverage
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To download this white paper, click here. » read more

Verifying Security Aspects of SoC Designs with Jasper App
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
By Various Writers - 15 Jan, 2014 - Comments: 1

Mobile systems require increasing data volume for multiple chip-to-chip interfaces. The high-speed MIPI® M-PHY is tailored for mobile systems where performance, power, and efficiency are key criteria. With up to 5,824 Mbps bandwidth, the speed meets devices’ high bandwidth and scalability requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications ... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 15 Jan, 2014 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a ... » read more

How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs
By Various Writers - 15 Jan, 2014 - Comments: 0

Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines ... » read more

Modern IC Packaging
By Various Writers - 18 Dec, 2013 - Comments: 0

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. To download this white paper, click here.  » read more

Accelerating Functional Closure
By Various Writers - 18 Dec, 2013 - Comments: 0

This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when... » read more

Solutions For Mixed-Signal SoC Verification Using Real Number Models
By Various Writers - 18 Dec, 2013 - Comments: 0

As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification. To view this white paper, click here. » read more

Automatic Macro Placement for Advanced Nodes
By Various Writers - 13 Dec, 2013 - Comments: 0

Finding the best placement for macros on a modern SoC can be serious challenge to design quality and cycle time.The Olympus-SoC place and route platform offers an automated and powerful solution for automatic macro placement (AMP) that significantly reduces the iterations and cycle time required to arrive at the optimal macro configuration. This paper describes the Olympus-SoC AMP technology an... » read more

Power And Signal Line Electro-migration Design And Reliability Validation Challenges For The 28nm Era
By Various Writers - 06 Dec, 2013 - Comments: 0

Reliability verification is an important aspect in the design and development of an integrated circuit (IC) to help guarantee its continued functionality over years of production use. One critical area of reliability verification is the electro-migration check analysis to ensure that the wires and vias used to connect the various devices in the chip do not fail from years of continuous use. ... » read more

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