System-Level Design
WHITEPAPERS

Accelerating Functional Closure

This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure

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This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage, and use it to achieve functional closure.

To view this white paper, click here.



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