How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs

A look at some of the challenges in reducing power and how to overcome those challenges.


Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost.

With the continuous increase of component density in ICs and the associated increase of power density, power consumption can become a real headache for designers. The challenge is to pack in more and more logic while still consuming less and less power. Semiconductor industry projections indicate an increase in leakage power for future technology nodes and all available techniques must be applied to meet the goal that average and standby power remain flat as complexity increases.

The goal for the designer is often to make power consumption as low as possible. However, this is just a part of the overall problem and there are more fundamental issues like functionality, testability, manufacturability, area and timing to be handled. To read more, click here.

Leave a Reply

(Note: This name will be displayed publicly)