Author's Latest Posts

Effective Post-TSV-DRIE Wet Clean Process For Through Silicon Via Applications
By Veeco - 18 Mar, 2020 - Comments: 0

Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen... » read more

Accelerating Silicon Carbide Power Electronics Devices Into High Volume Manufacturing With Mechanical Dicing System
By Veeco - 16 Dec, 2019 - Comments: 0

Silicon carbide (SiC) is a wideband gap semiconductor material that has huge potential to enrich our lives by enabling better technology with improved connectivity and efficiency. It offers many advantages over common silicon (Si) for power applications as it can be doped much higher than silicon to achieve optimal blocking voltage. In addition, SiC high thermal conductivity characteristic enab... » read more

Process To Produce High Aspect Ratio Electroplated Copper Pillars On 300 mm Wafers
By Veeco - 16 Oct, 2019 - Comments: 0

This work provides details of a complete and partially optimized process to manufacture high aspect ratio copper pillars with heights of up to 80 µm on 200 and 300 mm wafers. Across wafer uniformity data for all materials and process steps are given. Results will show excellent resist adhesion on copper and electroplating durability. Cross sectional SEM analysis of resist and electroplated pil... » read more

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology
By Veeco - 18 Sep, 2019 - Comments: 0

Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

Intra-Field Stress Impact on Global Wafer Deformation
By Veeco - 14 Aug, 2019 - Comments: 0

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane disto... » read more

Improvement Of Dopant Concentration Control With Acoustic Control System For B-SiGe Epitaxy Deposition
By Veeco - 19 Jun, 2019 - Comments: 0

Currently, SiGe-B epitaxy is a leading technology to induce strain in PMOS channel and improve the hole mobility to achieve better device performance. In practice, we observe that the device performance strongly depends on the dopant concentration, especially boron concentration. It is shown that the Acoustic Control System [ACS] is able to actively respond to instantaneous variations of incomi... » read more

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material
By Veeco - 22 May, 2019 - Comments: 0

Authors: Warren W. Flack, Robert Hsieh, Ha-Ai Nguyen Ultratech, a division of Veeco 3050 Zanker Road, San Jose, CA 95134 USA [email protected] John Slabbekoorn, Samuel Suhard, Andy Miller IMEC Kapeldreef 75 B-3001 Leuven, Belgium [email protected] Akito Hiro, Romain Ridremont JSR MICRO NV Technologielaan 8 B-3001 Leuven, Belgium [email protected] Abstract This... » read more

Lithography Challenges For Leading Edge 3D Packaging Applications
By Veeco - 18 Apr, 2019 - Comments: 0

Leading edge consumer electronic products drive demand for enhanced performance and small form factors. This in turn drives manufacturing requirements for all aspects of semiconductor device fabrication. As the cost of front end device manufacturing continues to escalate rapidly with each new technology node, semiconductor manufacturing companies are now also focusing on packaging technology to... » read more

Low Ripple Notch Filter Designs Using Apodized Thickness Modulation
By Veeco - 21 Mar, 2019 - Comments: 0

An apodized discrete layer thickness design method for notch filters is presented. The method produces error tolerant designs with low ripple in the pass band regions without any additional numerical optimization. Sample designs are presented. Multiple approaches have been used in the past for producing notch filters (also called minus filters). The two main approaches can be grouped into ru... » read more

Ion Beam Sputtering Deposition of Fluoride Thin Films
By Veeco - 12 Feb, 2019 - Comments: 0

By Aiko Ode, Veeco Instruments Thin film coatings for deep UV wavelengths are predominately produced by evaporation methods (thermal and Ebeam). Factors limiting the performance of evaporated films include surface roughness, porosity, absorption, and defect density. To enhance the films, they are typically deposited at high substrate temperatures (above 300°C.) The thermal stress created u... » read more

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