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External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology

Advanced nodes could benefit from nanosecond laser annealing of S/D structures, which produce a significant pFET external resistance reduction and corresponding RON decrease.

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Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo
1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: olegg@us.ibm.com
2GLOBALFOUNDRIES Inc., Albany, NY, USA,
3ULTRATECH, a division of VEECO INSTRUMENTS Inc., San Jose, CA, USA

We report on a significant pFET external resistance reduction (~40%) and corresponding 10% RON decrease by nanosecond laser annealing of S/D structures applicable to advanced technology nodes. Selective melting of pFET S/D elements is responsible for this improvement. Process window boundaries are defined by channel and junction melting at the upper end and by S/D SiGe melting at the lower end. Short channel characteristics are not degraded within the identified process window. Contacted gate pitch (CPP) and fin number dependence of the process window is assessed.

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