Advanced nodes could benefit from nanosecond laser annealing of S/D structures, which produce a significant pFET external resistance reduction and corresponding RON decrease.
Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo
1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected]
2GLOBALFOUNDRIES Inc., Albany, NY, USA,
3ULTRATECH, a division of VEECO INSTRUMENTS Inc., San Jose, CA, USA
We report on a significant pFET external resistance reduction (~40%) and corresponding 10% RON decrease by nanosecond laser annealing of S/D structures applicable to advanced technology nodes. Selective melting of pFET S/D elements is responsible for this improvement. Process window boundaries are defined by channel and junction melting at the upper end and by S/D SiGe melting at the lower end. Short channel characteristics are not degraded within the identified process window. Contacted gate pitch (CPP) and fin number dependence of the process window is assessed.
Click here to read more.
Less precision equals lower power, but standards are required to make this work.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
Wafer manufacturing and GPUs draw investment; 106 companies raise $2.8B.
Heterogenous integration depends on reliable TSVs, microbumps, vias, lines, and hybrid bonds — and time to digest all the options.
How prepared the EDA community is to address upcoming challenges isn’t clear.
Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
Details on more than $500B in new investments by nearly 50 companies; what’s behind the expansion frenzy, why now, and challenges ahead.
From specific design team skills, to organizational and economic impacts, the move to bespoke silicon is shaking things up.
Less precision equals lower power, but standards are required to make this work.
New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
Leave a Reply