Lithography Challenges For Leading Edge 3D Packaging Applications

Simpler single pass topside test can provide reasonable accuracy for monitoring processes that align to embedded targets.


Leading edge consumer electronic products drive demand for enhanced performance and small form factors. This in turn drives manufacturing requirements for all aspects of semiconductor device fabrication. As the cost of front end device manufacturing continues to escalate rapidly with each new technology node, semiconductor manufacturing companies are now also focusing on packaging technology to deliver improved performance and reduced form factor. A number of innovative technologies are being developed to support increasing packaging density requirements. It is anticipated that advanced three dimensional (3D) packaging technologies such as TSV (Through Silicon Via) manufacturing will play a critical role in future semiconductor device miniaturization. Advanced system in package (SiP) capability is now viewed as a key strategic technology by device manufacturers and foundry companies. Several SiP techniques will require TSV to provide high density vertical interchip wiring of multiple device stacks. These vias need to be freely placed in the device which creates a requirement for tight registration of the back-to-front side device alignment. This paper investigates the lithography challenges associated with TSV fabrication for various devices structures.

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