Verification is only as good as the specification that’s available, and if specs are incomplete then design and verification cycles will grow.
The rapid growth in complexity and size of modern System on Chip devices (SoCs), along with the expense of developing these ICs, has driven the need for design reusability. Today, SoC designs are typically built as a collection of individual IP (Intellectual Property) blocks stitched together with glue logic. These IP can be sourced from multiple design teams, including many 3rd-party teams. SoC (and IP) design and verification may also be subdivided into two distinct groups – RTL design and RTL verification. This division of labor enables specialization, but also divides design knowledge, which in turn complicates IP-SoC integration (and IP-level verification).
The job of the verification engineer is to verify that the RTL of the design, IP and / or SoC is functionally correct. With the division of knowledge, the verification engineer must increasingly rely on design specifications. Regardless of the verification technologies used, and the speed that it operates, this verification is only as good as the specifications available. If these specifications are incomplete, design and verification cycles will grow, and the production of a bug-free chip will become less likely.
Embedded assertions have long been a promising technology to address this division of knowledge. Yet this technology has fallen short due to the painful process of manually creating assertions. With the availability of automation, however, this promise can be fulfilled. To read more, click here.
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