Why the Big Players Like 450mm Wafers

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand:  bigger wafers should lower the per-chip cost of manufacturing.  But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography.  Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the overall costs.  A corollary to this economic reality is that as lithography costs go up as a fraction of the total costs, the benefits of a larger wafer size go down.  Past wafer size transitions have netted a 30% manufacturing cost reduction.  The transition to 450-mm wafers will give at best a 20% cost reduction, and possibly only a 10% reduction.

Of course, these numbers are projections, and all projections are based on assumptions.  It is possible to make more optimistic assumptions than I have, and that is probably what Intel, TSMC and the other big players are doing when they heavily promote 450-mm wafers.  But why are the big guys so optimistic about 450-mm wafers?  And why now?

As I briefly mentioned in my last post, for the switch to larger wafer sizes to be economically feasible two things must happen.  First, the switch must enable a lower manufacturing cost per chip.  The big players are hoping for a 30% cost reduction, but I am predicting a 10 – 20% benefit.  Second, there must be sufficient demand for the chips being produced to justify a higher volume factory.  A 450-mm fab will have at least double the output (in terms of chips) as a 300-mm fab.  Thus, the demand for those chips must at least double to justify the building of a 450-mm fab.  That’s a huge volume of chips, since 300-mm fabs are already exceedingly high-volume.

So an important effect of each wafer transition is that low-volume manufacturers can no longer compete.  A 30% cost disadvantage is hard to overcome, and without the volume demand a new fab at the larger wafer size isn’t justified.  The result?  A successful wafer size transition is accompanied by a host of consolidations and chip companies going fabless (or fab-lite).  This has happened again and again over the years.  Only the biggest players survive, and the survivors get bigger.

Today, we have Intel, Samsung, Toshiba and TSMC at the top of the chip-making pyramid.  But UMC, GlobalFoundries, Hynix, and Micron remain competitive irritants.  What to do?  A successful transition to 450-mm wafers will likely solve the problem for the big players.  If 450-mm wafers result in a 20 – 30% cost advantage over 300-mm wafers, then any standard-process chip in a cost competitive space will have to be made in a 450-mm fab.  But only a few of these $10B fabs will have to be built to supply that demand.  And those fabs will be built by the biggest players, leaving the second tier manufacturers out of luck, and possibly out of business.

So why shouldn’t Intel, Samsung, and TSMC be bullish on 450-mm?  If it works, it will mean that their dominance in the semiconductor world will be complete (maybe even pushing Toshiba out of the picture).  And if EUV succeeds in keeping litho costs down, this scenario is all the more likely.

But personally I don’t think EUV will be successful at putting a lid on litho cost.  As a result, I think the cost advantage of 450-mm will be closer to 10% than the 20 – 30% hoped for by the big guys.  And while 10% may still be worth it for the highest-volume players, it won’t be enough to put the 300-mm fab world out of business.

That leaves one more ugly point to consider.  If a transition to 450-mm wafers gives a per-chip cost reduction that is not sufficiently large to counter the rising costs of litho, then the per-chip costs overall might be higher (and maybe a lot higher) for new technology nodes.  What will happen to Moore’s Law if moving to the next node no longer decreases the cost of a transistor?

We live in interesting times, and getting more interesting each day.