BIST For Low-Power Devices

By Stephen Pateras
The persistent growth of mobile computing is driving an increasing need to manage power consumption within semiconductor devices. This has significant implications on the design and test of these devices. Low-power requirements affect test in two separate ways. First, it’s important to ensure that any functional power constraints are met (or at least adequately managed) during test execution. Second, it’s necessary to ensure that a test solution is compatible with whatever low-power design techniques are being used.

The first requirement has generally translated to ensuring circuit switching activity levels are maintained below a functionally defined threshold during scan test pattern application. This is accomplished by generating the scan test patterns in such a way as to control the number of 1 to 0 and 0 to 1 transitions within each pattern. The transition frequency corresponds directly to circuit toggle activity and thus to average power. Controlling the number of transitions is relatively straightforward for deterministically generated patterns. In the case of logic BIST however, patterns are generated on-chip using a pseudo-random pattern generator (PRPG), which makes controlling the number of transitions within each pattern more complicated. By definition, each pseudo-random pattern inherently has a transition frequency of 50%. Some form of post processing of the pattern data generated by the PRPG is therefore required.

Figure 1. Low-power logic BIST architecture.

The approach used by a recently introduced commercial low-power logic BIST solution is illustrated in figure 1. Each PRPG output produces a stream of pseudo-random bits. These bit streams are fed into a phase shifter to produce a much larger number of pseudo-random bit streams to feed each of the individual scan chains within the circuit under test. To reduce the inherent toggle rate of each bit stream, a holding register is placed between each PRPG output and the phase shifter. A low-power LBIST module individually controls each of these holding registers. This module accepts a target transition frequency as input, and based on probabilistic techniques, periodically forces each of the holding registers to maintain its current value for a certain number of cycles. This produces bit streams that together produce an average transition frequency over the entire circuit under test equal to the desired target.

In addition to having BIST solutions operate under functional power constraints, it is important that these solutions operate correctly in the presence of low-power design features. A good example of where this requirement is important is in relation to on-chip memory repair. Most commercial memory BIST solutions now support some form of Built-In Self-Repair (BISR). Having the ability to repair embedded memoires by swapping out defective rows or columns is becoming increasingly important to achieve adequate yield levels as the size and densities of embedded memories continue to grow. A typical self-repair architecture consists of an eFuse array to store repair information, a repair register placed next to each repairable memory for locally storing the necessary repair data, and a fuse controller for transferring data between the eFuse array and each of the repair registers. All of the repair registers throughout the chip are typically placed on a serial chain in order to minimize routing. When the device is powered up, the fuse controller reads the repair info from the eFuse array and scans it into all of the repair registers.

However, this self-repair architecture breaks down when voltage islands or power domains are used. This increasing popular power management approach involves using a separate supply voltage for each core (or, possibly, group of cores) within a design. Each resulting power domain can then be shut down when not in use and re-activated when needed. This powering up and down activity has a direct effect on repairable memories. When a sleeping power domain is re-activated, the repair information for the repairable memories in that domain will have been lost and will need to be reloaded. The challenge here is that the reloading has to occur without disrupting the already active domains, and the reloading can’t be affected by the fact that some domains may still be inactive.

Figure 2. Power-aware built-in self repair.

To handle these constraints, the self-repair architecture described above has to be augmented to provide at least one repair shift chain for each power domain, as illustrated in figure 2. Each shift register can be of arbitrary length. A functional power management unit indicates to the fuse controller which shift register(s) need to be loaded. The other shift registers are kept in a stable state as they might contain repair information of active power domains. When multiple domains are re-activated, the controller will generally need to load them sequentially according to a default priority defined at design time. The operation is sequential because all repair information is typically stored in the same eFuse array. If the loading order needs to be changed, the power management unit simply needs to re-activate each island one at a time in the desired order. The functional power management unit and the fuse controller must both be in an always-on power domain while the various memory BIST controllers and repair registers are placed within the same power domains as the memories they service. Power domains can span multiple physical regions (shown as blocks in figure 2) and a physical region can also contain multiple power domains.

It is clear that low-power requirements are becoming increasingly widespread. As with other parts of the semiconductor ecosystem, BIST solutions are evolving to meet the demands of advanced low-power design.

—Stephen Pateras is product marketing director within the Mentor Graphics Silicon Test Solutions group.