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Blog Review: April 6

More specialized AI IP; formal for RISC-V; UCIe; AI workloads.

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Synopsys’ Ron Lowman considers the increase in specialized AI IP in SoCs, including the different aspects within AI classifications, markets that are driving its growth, key SoC design challenges, and nurturing SoC designs beyond integration.

Siemens’ Joe Hupcey III finds that the only way to be completely sure that RISC-V RTL is free of any natural or malicious surprises is to apply exhaustive, formal methods to verify the design and recommends a formal-based flow.

Cadence’s Paul McLellan checks out the new Universal Chiplet Interconnect Express (UCIe) specification that aims to make it easier to ensure chiplets from different companies will work together in a multi-die package.

In a podcast, Arm’s Geof Wheelwright chats with Dennis Laudick about recent advancements in AI, the role specialized compute plays in enabling flexible approaches to run AI workloads efficiency from cloud to endpoint, and examples of advanced AI in action.

Coventor’s Assawer Soussou investigates the possibility of using a semi-damascene approach with self-aligned patterning for BEOL at the 1.5nm node and the process modifications that will be needed to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes.

Electronics & Radar Development Establishment’s Ashutosh Kedar and Ansys’ Nijas Kunju and Sharon Varghese consider challenges in designing phase array antenna systems, such as aiming the radiation pattern, antenna-antenna interaction, and antenna-platform interactions, and how 3D electromagnetic simulation can help.

SEMI’s Shari Liss argues that boosting the semiconductor industry workforce will require increased industry visibility, stronger investments in K-12 STEM education, and a greater focus on diversity, equity, and inclusion in the industry.

For a change from reading, check out a recent video:

Moving Intelligence To The Edge shows how moving increasing amounts of data is inefficient.

A lack of standardized formats makes it difficult to track IP throughout an organization, in Cataloging IP In The Enterprise.

Why nanosheets and gate-all-around FETs are the next big shift in Next-Gen Transistor structures.

Why Traceability Matters for staying on track with initial specs in complex heterogeneous designs.

The Ethernet Evolution and why this technology has continue to thrive in data centers.

Design Technology Co-Optimization can lead to fewer surprises, better results, and faster time to market.

Things that can go very wrong in a large, complex chip design include The Risk Of Losing Track Of Your IP.



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