Blog Review: Aug. 2

Die attach thermal testing; ESD damage; generative AI design; digital twins.


Siemens’ Katie Tormala points to the need for die attach thermal testing to ensure efficient removal of heat dissipation from power electronics components to prevent premature failure or thermal runaway.

Synopsys’s Dermott Lynch notes that over 30% of semiconductor failures are attributed to electrostatic discharge, with damage ranging from leakages and shorts to junction and metallization burnouts, gate oxide ruptures, and resistor-metal interface deterioration.

Cadence’s Reela Samuel listens in on a panel discussing the possibilities of generative AI in design and the impact of possible errors on chip development.

Keysight’s Mike Hodge explains why digital twins are different from models or 3D simulations and explores some of the use cases and applications.

Codasip’s Mike Eftimakis argues against relying solely on PPA numbers to choose a digital IP because meaningful comparisons are impossible and benchmarks are not usually directly applicable to a product and use case.

Arm’s Mo Jabbari introduces the Arm RAN Acceleration Library, a software library that provides optimized signal processing and related math functions for enabling 5G RAN deployments by leveraging the vector engines to accelerate 5G NR and LTE signal processing workloads, such as vector/matrix manipulation, channel coding, modulation, and FFT.

Ansys’ Sanjay Gangadhara examines the technical factors driving transformation in the photonics space, from component miniaturization through use of microstructures to changing workflows.

The ESD Alliance’s Bob Smith chats with John Lee of Ansys about why 3D-IC is growing and the role of foundries in industry collaboration.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Virtual conferences are in the rear-view mirror, but Technology Editor Brian Bailey is not convinced in-person conferences should continue.

Expedera’s Pat Donnelly looks at increasing NPU utilization by optimizing the flow of activations through a network.

Arteris’ Frank Schirrmeister predicts that AI, chiplets, and increasing integration mean design methodologies could look very different in the next decade.

Siemens’ Dina Medhat contends that deploying physical verification techniques in isolation will not solve the challenges of densely packed designs.

Keysight’s Sarah LaSelva foresees that a combination of large data sets and complexity will make wireless networks ripe for AI optimization.

Codasip’s Zdeněk Přikryl suggests enabling a compiler to use both standard and custom RISC-V instructions automatically and wisely.

Synopsys’ Taruna Reddy finds that distributed simulation enables a large job to be run in smaller parts.

Cadence’s Yang Zhan explains why network speed is one of the most significant limiting factors for generative AI.

Leave a Reply

(Note: This name will be displayed publicly)