Blog Review: Aug. 5

Fresh from the July 2015 Type-C InterOp Event, where USB engineers wheel a prototype on a cart from hotel room to hotel room, testing interoperability, Synopsys’ Morten Christiansen says Type-C has arrived.

Mentor’s Colin Walls discusses the reasons to tackle embedded software development with a bottom-up approach.

In their latest video, Cadence’s Kishore Kasamsetty discusses why choose LPDDR4 for automotive memory designs.

From electronic umpires to a bed that’s sure to wake you up, ARM’s Brian Fuller rounds up this week’s tech news.

There’s plenty of summer fun from Ansys’ Justin Nescott in his picks for this week’s top articles: London’s giant slide, an electric racecar breaks the world record for acceleration, plus a helmet to keep athletes cool.

While most of the discussion around Moore’s Law focuses on logic chips, Rambus’ Aharon Etengoff highlights its role in memories.

Companies, social media, and apps collect our data. NXP’s Martijn van der Linden reports on a MWC panel discussing what approaches companies could take to turn data collection from a perceived threat into an opportunity.

The White House’s Jo Handelsman and Eleanor Celeste took a trip to the National Institute of Standards and Technology to see the metrology center’s work on redefining the kilogram.

Aldec’s Satyam Jani digs into the less talked about areas of code coverage, and how they can enhance the coverage analysis process.

From the Silicon Innovation Forum, Applied’s Tony Chao has a look at the VC ecosystem around the semiconductor industry.

For some more reading, check out the blogs featured in last week’s System-Level Design newsletter:

Editor in Chief Ed Sperling looks at where the next big push will come from in semiconductors and why.

Mentor’s Yuansheng Ma observes there are still some problems to work out, such as cutting defect rates, but directed self-assembly is looking very attractive.

eSilicon’s Mike Gianfagna warns that monopolies can happen far faster in the custom chip market because there are fewer players.

Arteris’ Kurt Shuler contends that assessing IP quality should be the top priority for SoC design teams weighing time-to-market risk factors against configurability.

Cadence’s Frank Schirrmeister notes that the integration between verification engines is in full swing, with more to come.

Synopsys’ Tom De Schutter finds that in a battle of robots, picking winners isn’t always so obvious.