Blog Review: Dec. 2

Mentor’s Harry Foster investigates the effectiveness of today’s FPGA verification processes in terms of nontrivial bug escapes into production as part of the 2020 Wilson Research Group Functional Verification Study.

Synopsys’ Chris Clark points to how integral sensors are to the modern vehicle and key design considerations for making them more effective, safe, and reliable.

Cadence’s Paul McLellan takes a look at how STMicroelectronics determined whether formal would be effective for verification of its digital IP blocks and how it compared to constrained random.

Arm’s Jade Alglave and Nikos Nikoleris explain how to run litmus tests on hardware using litmus7 to help verification engineers test whether their implementation follows the Arm architecture and memory model.

Ansys’ Peter Hallschmid and Ellen Schelew explore why a well-defined workflow centered around statistically enabled compact models is key to successful photonics design and manufacturing.

SEMI’s Clark Tseng finds that in spite of the issues in the global economy, semiconductor sales and equipment billing soared in September with the equipment market expected to reach a new high this year.

In a video, VLSI Research’s Dan Hutcheson chats with Jim Handy of Objective Analysis about the state of the memory market, how the year played out differently from expectations, and what looks to be ahead for DRAM and NAND in 2021.

Verification blogger Tudor Timi compares formal and simulation by taking a single design and setting up two verification environments and finds that formal pushes a different way of thinking about designing testbenches.

NXP’s Peter Pirc considers some of the use cases of UWB wireless technology and how it compares with Bluetooth, Wi-Fi, and other connectivity options.

For a change from reading, check out a recent video:

Silicon Lifecycle Management explores mapping, tracking and reacting to changes throughout a chip’s expected lifetime.

Balancing performance through hardware-software co-design with flexibility in design can provide Faster Inferencing At The Edge.

Using data from multiple sources to improve yield, with the help of Virtual Fabrication At 7/5/3nm.

How to ensure consistent performance in the real world by focusing on 112G SerDes Reliability.

New structures, processes and yield/performance issues are among the Challenges At 3/2nm.

Understand what’s important for making tradeoffs in AI Inference Acceleration.