Blog Review: Feb. 24

Siemens EDA’s Harry Foster checks out the efficiency and effectiveness of verification on ASIC and IC designs with a look at how many projects meet the original schedule, the number of required spins, and classification of functional bugs.

Cadence’s Paul McLellan listens in as Philippe Magarshack of ST Microelectronics on how the company uses massive amounts of data generated by its fabs to power digital twins and optimize things from the shop flow to design for manufacturing.

A Synopsys writer checks out what’s new in CXL 2.0 for device discovery, with multiple new PCIe designated vendor-specific extended capabilities in the PCIe configuration space mapped registers.

Arm’s Roberto Lopez Mendez provides some tips on getting the most out of the Arm NN inference engine when running on GPUs by enabling some new features to significantly reduce memory usage and achieve a substantial inference speed-up.

Lam Research’s Nerissa Draeger shares some of the best practices the company has developed for successful collaboration with academic partners, including having a clearly defined problem and research approach and full transparency in methods and results.

SEMI’s Bettina Weiss investigates the semiconductor shortage currently hampering global automotive production and why automakers need to interact and collaborate more closely with the semiconductor supply chain.

Ansys’ Theresa Duncan shows improvements to a workflow for better ensuring electronic reliability, including a meshing engine for complex PCB models.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Executive Editor Mark LaPedus examines GlobalWafers’ move to buy rival Siltronic amid booming wafer demand.

Amkor’s Shaun Bowers digs into packaging changes required for wide-bandgap devices.

Quik-Pak’s Ken Molitor looks at the impact of small-form-factor packages on 5G electrical and thermal performance.

SEMI’s Christian Dieseldorff observes that from 2019 through the end of 2021, China will have increased wafer capacity for memory by 95%, foundry by 47%, and analog by 29%.