A Design Flow For Critical Embedded Systems

Learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems. Includes usage of these capabilities integrated using Arteris SoC integration technology: HW/SW codesign RTL, SystemC TLM and PSL Instruction Set Simulators Click here to read more. » read more

Journey From Cell-Aware To Device-Aware Testing Begins

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Week In Review: Semiconductor Manufacturing, Test

The U.S. Commerce Department outlined proposed rules for the Chips for America Incentives Program, including additional details on national security measures applicable to the CHIPS Incentives Program included in the CHIPS and Science Act. The rules limit funding recipients from investing in the expansion of semiconductor manufacturing in foreign countries of concern, notably the People’s Rep... » read more

Thermally Optimizing A High-Power PCB

The growth of battery-powered applications is presenting new challenges for designers of electronic motor-driven solutions. Targeting higher performance and efficiency, the power stages of these products must manage high currents while meeting strict power dissipation and size requirements. This white paper illustrates a thermally aware workflow with the Cadence® Celsius™ Thermal Solver... » read more

Week In Review: Auto, Security, Pervasive Computing

Automotive, mobility Cadence is now an official technology partner of the McLaren Formula 1 Team. The team will use Cadence’s Fidelity CFD Software to look at the computational fluid dynamics (CFD) of the airflow around the race cars and predict how a car design will affect the airflow. Infineon uncorked its XENSIV 60 GHz automotive radar sensor for in-cabin monitoring systems. One use ca... » read more

Chemistry Working For Lithography: The Marangoni-Effect-Based Single Layer For Enhanced Planarization

In the field of semiconductor manufacturing, there is still a continuous search for techniques to improve the Critical Dimension Uniformity (CDU) across the wafer. CDU improvement and general defectiveness reduction increase the industrial yield and guarantee high reliability standards. In the KrF Dual-Damascene module integration, at a lithographic level, deep trench planarization is mandatory... » read more

Week In Review: Auto, Security, Pervasive Computing

Automotive Cadence announced its new platform for speeding up the creation of virtual and hybrid prototypes of complex systems, such as those found in automotive systems. The Cadence Helium Virtual and Hybrid Studio enables teams to verify embedded software and firmware on virtual and hybrid configurations before the RTL is ready, in systems where software and hardware need to be created simul... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonst... » read more

Week In Review: Auto, Security, Pervasive Computing

Automotive/Mobility Chip-telemetry company proteanTecs has joined TSMC’s IP Alliance Program, which puts proteanTecs’ Universal Chip Telemetry (UCT) IP into TSMC’s catalog of production-proven IP. UCT is a monitoring system designed directly into chips to pull measurements from inside the chip throughout its lifecycle, including after placement in systems in the field. Monitoring the hea... » read more

Blog Review: Feb. 24

Siemens EDA's Harry Foster checks out the efficiency and effectiveness of verification on ASIC and IC designs with a look at how many projects meet the original schedule, the number of required spins, and classification of functional bugs. Cadence's Paul McLellan listens in as Philippe Magarshack of ST Microelectronics on how the company uses massive amounts of data generated by its fabs to ... » read more

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