Blog Review: Jan. 18

Post-quantum security; verification technology adoption; UCIe; line edge roughness.


Synopsys’ Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions.

Siemens EDA’s Harry Foster looks at trends in adoption of verification technologies for ASIC designs, including dynamic techniques, static technologies, and emulation and FPGA prototyping.

Cadence’s J. Harshit provides a brief introduction to the UCIe specification, which provides a common chiplet interconnect that enables the construction of large SoCs that exceed the maximum reticle size.

Renesas’ Makiko Seki explains the Safety Integrity Level, a measure of autonomous and semi-autonomous safety system performance in terms of the probability of failure, and the process of designing a system for compliance.

Riscure’s Marc Witteman checks out differential fault analysis in cryptographic implementations and exploitation of persistent faults, which may be more easily applied than transient faults since they do not require precise timing and stay active for a longer period.

Ansys’ Naseem Ansari explains the Reynolds number, an important dimensionless parameter used in fluid mechanics to help predict the behavior of fluids, and how to calculate it.

Coventor’s Sumant Sarkar shows how modeling line edge roughness (LER) can help engineers develop process specifications to achieve their targeted yield.

In a podcast, Arm’s Geof Wheelwright and Dermot O’Driscoll chat about the changing design requirements in the data center and infrastructure space, along with the importance of efficient hardware along with developer platforms and a software ecosystem.

In a blog for SEMI, DataProphet’s Nicol Ritchie suggests that deployment of AI could provide semiconductor manufacturers operational gains by identifying defective chips and determining the quality of wafers.

Verification blogger Tudor Timi demonstrates how to reap the benefits of dynamic test creation in UVM with an alternative way of defining tests.

Nvidia’s Amanda Saunders predicts edge AI development in 2023 will focus on use cases with high ROI, more human-machine collaboration, industrial safety, cybersecurity, and digital twins.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Lou Ternullo points out the latest updates to the PCIe specification, which are essential for devices that require the movement of large amounts of data.

Synopsys’ Gordon Cooper details a new class of neural network models that are opening the door to full visual perception.

Quadric’s Steve Roddy looks at how to avoid getting stranded on the machine learning roadside.

Arm’s Ashok Bhat explains how artificial intelligence (AI) can be part of the solution for tackling global warming, but admits it’s also a significant emitter of carbon itself.

Siemens’ John Wagnon examines how to predict and prevent electromigration and IR drop effects in FPGA designs.

Cadence’s Veena Parthan shows how to simplify import and preparation of geometry, as well as surface and volume meshing.

Ansys’ Laura Carter finds a better way to build batteries for off-road bikes.

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