Blog Review: Jan. 3

Signal integrity challenges; Intel’s 10nm; DFT methodologies; quantum computing.


Ansys’ Steve Pytel argues that increased signaling speeds and frequencies have led to signal integrity issues that circuit simulation alone cannot handle.

Cadence’s Paul McLellan dives into the details of Intel’s 10nm process, including three layers of self-aligned quadruple patterning, contact-over-active-gate, and cobalt for contact fill.

Mentor’s Ron Press and Vidya Neerkundar argue that with a growing number of DFT integration steps, adopting a DFT methodology with a well-defined infrastructure and automation is essential.

Synopsys’ Jim Ivers warns that to guard against being taken unaware by a vulnerability, it’s important to know what open source code is in a project.

Applied’s Sundeep Bajikar points to how AI applications will influence architectures and memory, with highlights from a chat with Jeff Welser of IBM.

In a video, VLSIresearch’s G. Dan Hutcheson sits down with Carl Williams of NIST to discuss the new world of quantum computing including when they will beat classical ones, new standards, and the global race for leadership.

Rambus’ Aharon Etengoff says it’s not enough to have just one layer of protection against side-channel attacks, and systems should be evaluated to make sure the countermeasures are effective.

A Lam Research writer shares highlights from the past year.

Mentor’s Anil Khanna notes that as cars move from internal combustion to electric, the way automakers deal with noise in the cabin is changing.

And don’t miss the blogs featured in the latest System-Level Design newsletter:

Editor in Chief Ed Sperling contends that a fundamental shift is underway in system-level design.

Technology Editor Brian Bailey looks back at which subjects garnered the most reader interest in 2017.

Mentor’s Ron Press and Vidya Neerkundar show how to improve the rate of success in the DFT flow.

Synopsys’ Malte Doerper examines ways to improve model quality with Agile methods and code analysis.

eSilicon’s Mike Gianfagna predicts that in 2018 there will be a lot more advanced ASICs targeting high-performance computing, deep learning and 5G infrastructure.

Cadence’s Frank Schirrmeister points to smarter ways to use verification.

OneSpin’s Saša Stamenković identifies a different kind of challenge for formal engineers.

Arm’s Ronan Synnott explains how to use the built-in performance analyzer in DS-5.

Aldec’s Henry Chan digs into FPGA prototyping and how to get them up and running more quickly.

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