Demand for verification engineers; retargeting older chips; RISC-V ecosystem; backside power delivery.
Siemens EDA’s Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers.
Synopsys’ Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity.
Cadence’s Paul McLellan shares highlights from the recent RISC-V Summit including the importance of ecosystems to growing adoption of the ISA, including efforts to bring Android to RISC-V.
Coventor’s Sandy Wen checks out the latest development in backside power delivery and the potential of buried power rails at the fin level.
Arm’s Sandeep Mistry explores developing with the Matter protocol with Bluetooth Low Energy commissioning and Wi-Fi using Arm Virtual Hardware.
Ansys’ Laura Carter checks out how radar chipsets that incorporate the Doppler effect into a phased array radar defined by an increase or decrease in wave frequency dictated by movement of a source toward or away from an object could help improve vehicle safety.
Renesas’ Graeme Clark shows how a Data Operating Circuit (DOC) and Data Transfer Controller (DTC) can be combined to create a complete, autonomous subsystem, that can operate without CPU intervention.
Codasip’s Lauranne Choquin shares several take aways from the recent RISC-V summit.
In a blog for SEMI, Rogue Valley Microdevices’ Jessica Gomez explains what smaller companies should know about the CHIPS Act and why forming partnerships will help in taking advantage of incentive programs.
Memory analyst Jim Handy wonders whether the recent declines in the price of DRAM and NAND are really unprecedented.
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