Blog Review: July 15

Synopsys’ Mike Borza explains DARPA’s Automatic Implementation of Secure Silicon (AISS) program and why prioritizing security in the chip development and manufacturing process is so important.

Mentor’s Jacob Wiltgen checks out how accurate early cycle safety analysis, aided by automation, can help avoid the problem of unmet safety goals and expensive later cycle iterations.

Cadence’s Paul McLellan considers Apple’s forthcoming switch to Arm-based chips for some Macs and what they may have to deal with in getting old software to run on the new architecture.

Arm’s Fabrice Dupros, Genci’s Christelle Piechurski, CEA’s Laurent Nguyen, and Atos’ Cyril Mazauric explain the process of porting and optimizing scientific research applications for Arm-based supercomputers.

VLSI Research’s Julian West finds that sales of abatement systems for semiconductor applications significantly outperformed other critical subsystems in 2019 and why adoption of EUV has helped push its growth.

Ansys’ Marc Swinnen points to how collaboration and tool integration enable 2.5D/3D IC packages with a single environment for design exploration, implementation, and signoff.

Memory analyst Jim Handy takes a look back at 68 years of FRAM, the first nonvolatile semiconductor memory, and why despite difficult and expensive fabrication requirements ferroelectric memory looks to be regaining popularity in research labs.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Editor in Chief Ed Sperling contends that performance is less of a problem in new devices than power — at least for now.

Rambus’ Frank Ferro explains why the memory developed for high-end graphics cards isn’t just for gaming anymore.

Adesto’s Tommy Mullane advises that on big chips, tools to support communication are a critical factor in success.

Cadence’s Thomas Wong lays out why, when it comes to die-to-die PHY interfaces, the best solution is highly dependent on the end application.

Mentor’s Terence Chen and Alexander Volkov describe a way to add simplicity, predictability, and flexibility to the physical implementation process.

The RIKEN Center’s Satoshi Matsuoka gives an insider’s view of the technology and collaboration between the new Arm-based supercomputer at RIKEN.

Moortec’s Tim Penhale-Jones spells out why getting at the truth of an SoC’s state calls for an impartial source of information.

Ansys’ Peter Hallschmid and Dylan McGuire demonstrate a flow to design and optimize gain elements and lasers on indium phosphide and gallium arsenide.

Johns Hopkins University’s Rama Chellappa asks why technical breakthroughs in the sensors-signals processing-decisions pipeline point to pervasive applications of AI.

proteanTecs’ Noam Brousard emphasizes the importance of making sure signals arrive not just in time, but on time.

Synopsys’ Himanshu Bhatt and Susantha Wijesekara talk about how to reduce the overall turnaround time for verification signoff while ensuring bugs don’t escape.

DAC’s Michelle Clancy sees trends in submitted papers that show what’s important to engineers as design flows increase in complexity.