Blog Review: July 17

Cadence’s Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency.

Synopsys’ Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new security features, extended meta data, and improved visibility into CXL memory device errors.

In a podcast, Siemens’ Steph Chavez, Andre Mosley, and Carlos Gazca chat about design reuse methodologies in EDA, including the challenges with data management and version control in circuit design and security concerns in design reuse, export control, and ITAR regulations.

Lam Research’s Dempsey Deng compares the parasitic capacitance of a 6F² honeycomb DRAM device to that of a 4F² vertical-channel-access-transistor (VCAT) DRAM structure, which shows significantly reduced parasitic capacitance between the node contacts and the bitlines.

Keysight’s Choon-Hin Chang suggests combining a PCB panelization manufacturing technique alongside a manufacturing parallel test system to optimize the testing process for high-volume, low-complexity PCBA.

Arm’s Tony Nip introduces AMBA Viz, a hardware verification tool for cycle-accurate RTL simulation and emulation that aims to make functional debug and performance analysis faster and more intuitive, even for complex Arm IP like CMN interconnects and AMBA bus protocols.

Ansys’ Mark Palmer considers obstacles to the adoption of computational methods by the healthcare sector, including regulatory acceptance and model credibility, and the market forces that are driving the need for further adoption of computer modeling and simulation.

SEMI’s Jaegwan Shim shares highlights from SMC Korea, including predictions on when gate-all-around and CFET devices will be available, a look at EUV dry resist technology, and the need for new materials for advanced packages.

For a change of pace, check out a recent video:

Errors in chiplets, automotive safety, processors become key targets for Changes In Formal Verification.

Promises And Pitfalls Of SoC Restructuring include the need to sidestep data incompatibility issues in heterogeneous chip designs.

Making Adaptive Test Work Better by managing more data efficiently.

Microcontrollers become key platform for machine learning with recent MCU Changes At The Edge.

Understanding Electromigration And IR Drop At Advanced Nodes helps achieve a DRC-clean, manufacturing-ready design.

Right-sizing chiplets and other components based on real workloads as part of Adapting To Evolving IC Requirements.

Sensor Fusion Challenges In Automotive and why a single, centralized architecture is so critical for sensors.

How analytics can improve yield in high-volume manufacturing of panels with Overlay Optimization In Advanced IC Substrates.

Secure Movement Of Data In Test and why heterogeneous integration changes how data is used in manufacturing.

The benefits and challenges in heterogeneous integration include Challenges With Chiplets And Power Delivery.

Challenges In RISC-V Verification include how to debug a multi-core chip and ensure it will be cache coherent and secure.

Cache Coherency In Heterogeneous Systems and why maintaining flexibility in coherency is essential.