Blog Review: Mar. 11

5G and edge processing; CXL device types; metrology limitations.


Rambus’ Steven Woo examines how the upcoming deployment of 5G will enable processing at the edge, and how the edge is getting refined further into the near edge and the far edge with a range of AI solutions across it.

A Synopsys writer explains the types of Compute Express Link devices and CXL’s unique verification challenges like maintaining the cache coherency between a host CPU and an accelerator.

Mentor’s Colin Walls considers different levels of precision and compromises and conversion between different types of floating point.

Cadence’s Paul McLellan looks at the implications of the FCC’s approval of a $9.7B incentive package for satellite companies using the 3.7GHz to 3.98GHz C-band to clear up spectrum for 5G.

In a video, VLSI Research’s Dan Hutcheson chats with Peter Jenkins of Infinitesima about the increasing importance of inspection and metrology and why new approaches are needed to overcome current limitations for current in-line metrology technologies.

SEMI’s Christian G. Dieseldorff predicts that while fab equipment spending will recover modestly this year, its set for new record highs in 2021 with several regions forecast to invest over 20% more and 3D NAND and DRAM equipment spending jumping 40%.

Arm’s Ronan Synnott provides a quick introduction on how to use Arm’s tools to develop with custom instructions.

Plus, check out the featured blogs from the latest Auto, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Editor In Chief Ed Sperling finds far fewer elbows to bump at semiconductor conferences.

Managing Editor Susan Rambo shows what International Women’s Day has to do with the semiconductor industry.

Rambus’ Paul Karazuba digs into why, from edge to data center, AI devices require specific security features to protect valuable training sets and data from attackers.

Mentor’s Chuck Battikha and Doug Smith explain how to simplify the FMEDA process and automatically compute failures in time rates for each design component.

Cadence’s Paul McLellan argues that questioning authority is an important part of avoiding social engineering attacks.

Editor In Chief Ed Sperling argues that just putting a chip on an ATE machine is no longer sufficient for many applications.

KLA’s Meng Zhu, Roman Sappey, and Jeff Barnum ask what MRAM is and why it is becoming more attractive to the industry.

Mentor’s Mohammed Abdelwahid examines an improvement to BiST that meets test coverage for ISO 26262.

YieldHub’s Marie Ryan digs into how using wafer acceptance testing to monitor the consistency of key parameters across a wafer can improve yield and reduce defects.

OptimalPlus’ Michael Schuldenfrei explains how using a communication framework that tracks an asset’s data throughout its lifecycle can be used to integrate traditionally siloed data into business operations.

FormFactor’s Amy Leong describes why making chiplets a mainstream technology relies on balancing the cost of test with yield risk.

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