Blog Review: March 2

Arm’s Charlotte Christopherson checks out SpiNNaker1, a project to develop a massively parallel, manycore supercomputer architecture that mimicked the interactions of biological neurons, and its follow up, SpiNNaker2, a hybrid system that combines statistical AI and neuromorphic computing.

Cadence’s Paul McLellan looks at open and generic PDKs that can be used by researchers and in education without costly licensing requirements or restrictions.

Siemens’ Jake Wiltgen finds that accurate safety planning and analysis, including failure mode effects diagnostic analysis, fault tree analysis, and determination of whether the safety architecture is sufficient, is critical to delivering a safe IC on time and on schedule.

Synopsys’ Emilie Viasnoff investigates how digital twins can be used in optics and photonics to improve an imaging system’s time to production, customize device performance for specific applications, and generate synthetic optical data.

Coventor’s Brian Van Dyk checks out how to build a 3D solid model of a MEMS device for finite element analysis using the 2D layout geometry file to eliminate the chance of inadvertent translation mistakes and speed up model generation.

Ansys’ Giovanni Petrone and Domenico Caridi introduce the basics of aeroacoustic simulation for automotive and how it can help identify the source of an unwanted sound and find ways to silence it.

In a blog for SEMI, Brewer Science’s Jessica Albright considers some of the challenges involved in maintaining a B Corp certification, from documentation to encouraging employees.

Memory analyst Jim Handy explains the ups and downs of the commodity cycle, how it relates to pricing and supply of memory chips, and why DRAM is like onions.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Editor-in-Chief Ed Sperling looks at Intel’s support for RISC-V marking a technological and cultural shift.

Technology Editor Brian Bailey finds plenty of misguided complaints across the industry.

Siemens’ Tarek Ramadan looks at ensuring the intended connectivity of the die, silicon interposer, and organic substrate.

Cadence’s Frank Schirrmeister examines how generational changes of the end customer base may impact electronics.

Synopsys’ Taruna Reddy shows how leveraging recorded signal activity from previous full-chip simulations accelerates time-to-debug.

Codasip’s Rupert Baines contends that for many systems, the best processor is one tailored for its task.